Abstract: The present disclosure presents systems and methods performing a simulation on a hybrid virtual system-on-chip (SoC) model. One such method comprises receiving a configuration file that identifies register transfer level (RTL) abstractions; virtual prototype abstractions; unit-level testbenches; place holder variables; and a shared interface among one or more hardware circuitry blocks designed as RTL abstractions and one or more hardware circuitry blocks designed as virtual prototype abstractions; creating the hybrid virtual SoC model based on the configuration file by instantiating the one or more hardware circuitry blocks designed as RTL abstractions and a stub hardware circuitry block for each of the one or more hardware circuitry blocks designed as virtual prototype abstractions; and integrating unit-level testbenches for the one or more hardware circuitry blocks represented as RTL abstractions.

Abstract: A system comprising a vehicle subsystem comprising a plurality of modules and a vehicle chassis, wherein the plurality of modules (i) comprises mechanical or electronic components that simulate one or more vehicle or vehicle electronic functionalities, (ii) comprises a modular form factor corresponding to the vehicle chassis, and (iii) is coupled to a vehicle computer; an attacker subsystem configured to attack a module of the plurality of modules; and a controller subsystem configured to control operation of the vehicle subsystem and the attacker subsystem by (i) providing (a) a vehicle control command to the vehicle subsystem and (b) an attacker control command to the attacker subsystem and (ii) receiving (a) vehicle feedback from the vehicle subsystem and (b) attacker feedback from the attacker subsystem.

Abstract: Disclosed are various embodiments related to coordinated monitoring and responding to an emergency situation at a building structure as a supplement to a traditional emergency response. In some embodiments, a system comprises a computing device that is configured to receive sensor data from a sensor network. The sensor network includes monitoring units that monitor various locations of an infrastructure. The computing device determines an occurrence of an emergency event at a location in the infrastructure using an anomaly detector model based at least in part on the sensor data. A hybrid mobile unit is instructed by the computing device to navigate to the location of the emergency event. The hybrid mobile unit is configured to provide mobile sensor data associated with the location to confirm the emergency event.

Abstract: A system for secure testing and provisioning of an integrated circuit (IC) includes, in part, a secure reconfigurable key provisioning architecture (SLEEVE) module disposed in the IC, and a secure asset provisioning hardware entity (SAPHE) module. The IC may include, in part, a modified IEEE 1500 wrapper to control its operation modes. The SLEEVE module may include, in part, an encoding/decoding module and an unlocking module. The encoding/decoding module may include, in part, a decode key stream cipher module, an encode key stream cipher module, Seed Key programmable linear-feedback shift registers (LFSRs), Initialization Vector (IV) LFSRs, and configuration registers. The encoding/decoding module may be configured to generate key bits for decoding and encoding inputs and outputs of the IC. The unlocking module may include, in part, a pattern matching block and a counter. The unlocking module may be configured to enable write access to the configuration registers.

Abstract: Various embodiments of the present disclosure provide functional verification flow of obfuscated designs for circuits. In one example, an embodiment provides for applying an input sequence to an obfuscated design for an integrated circuit that is formatted in a hardware description language, applying the input sequence to an original design for the integrated circuit that is formatted in the hardware description language, and comparing respective outputs provided by the obfuscated design and the original design to determine functional correctness of the obfuscated design.

Abstract: Various embodiments of the present disclosure provide for redacting Network-on-Chip (NoC) functionality in a System-on-Chip (SoC). In one example, an embodiment provides for receiving a Register Transfer Level (RTL) source code that models a design for an SoC via a hardware description language, converting one or more routing tables related to the RTL source code with one or more configurable logic tables, replacing one or more connections related to the RTL source code with one or more programmable multiplexers, generating a transformed RTL source code for the SoC based on the one or more configurable logic tables and the one or more programmable multiplexers, and/or providing an attack-resistant obfuscated SoC based on the transformed RTL source code.

Abstract: The present disclosure presents systems and methods performing a simulation on a hybrid virtual system-on-chip (SoC) model. One such method comprises receiving a configuration file that identifies register transfer level (RTL) abstractions; virtual prototype abstractions; unit-level testbenches; place holder variables; and a shared interface among one or more hardware circuitry blocks designed as RTL abstractions and one or more hardware circuitry blocks designed as virtual prototype abstractions; creating the hybrid virtual SoC model based on the configuration file by instantiating the one or more hardware circuitry blocks designed as RTL abstractions and a stub hardware circuitry block for each of the one or more hardware circuitry blocks designed as virtual prototype abstractions; and integrating unit-level testbenches for the one or more hardware circuitry blocks represented as RTL abstractions.

Abstract: A system for secure testing and provisioning of an integrated circuit (IC) includes, in part, a secure reconfigurable key provisioning architecture (SLEEVE) module disposed in the IC, and a secure asset provisioning hardware entity (SAPHE) module. The IC may include, in part, a modified IEEE 1500 wrapper to control its operation modes. The SLEEVE module may include, in part, an encoding/decoding module and an unlocking module. The encoding/decoding module may include, in part, a decode key stream cipher module, an encode key stream cipher module, Seed Key programmable linear-feedback shift registers (LFSRs), Initialization Vector (IV) LFSRs, and configuration registers. The encoding/decoding module may be configured to generate key bits for decoding and encoding inputs and outputs of the IC. The unlocking module may include, in part, a pattern matching block and a counter. The unlocking module may be configured to enable write access to the configuration registers.

Abstract: Disclosed are various embodiments related to coordinated monitoring and responding to an emergency situation at a building structure as a supplement to a traditional emergency response. In some embodiments, a system comprises a computing device that is configured to receive sensor data from a sensor network. The sensor network includes monitoring units that monitor various locations of an infrastructure. The computing device determines an occurrence of an emergency event at a location in the infrastructure using an anomaly detector model based at least in part on the sensor data. A hybrid mobile unit is instructed by the computing device to navigate to the location of the emergency event. The hybrid mobile unit is configured to provide mobile sensor data associated with the location to confirm the emergency event.

Abstract: Systems and methods generate the design of a tiled multi-core system-on-chip (SoC). Design specification defining a multitude of cores to be used in the tiled multi-core SoC is analyzed and a multitude of subsystems based on the plurality of cores is built. The subsystems are augmented with one or more network adapters to generate the design of the tiled multi-core SoC. To achieve this, a multitude of IP blocks defined by the specification are retrieved from a design library. Design metadata associated with the IP blocks are extracted. Next, a standardized interface is generated for each of the IP blocks using the design metadata. Thereafter, a bus interface is generated for the IP blocks. Next, a tiled synthesizable register-transfer level code for the SoC design is generated in accordance with received configuration information.

Abstract: Various examples are provided related to multi-purpose context-aware bumps (CABs) that can support dynamic adaptation of form factors and functionality. In one example, a CAB system can include sensors distributed in a traffic network and communicatively coupled to a remotely located computing environment; context-aware bumps (CABs) placed in the traffic network and communicatively coupled to the remotely located computing environment; and a CAB application configured to adjust a form factor of a CAB in response to information obtained from the sensors and/or CABs. In another example, a method can include receiving, by a remotely located computing environment, traffic information from sensors distributed in a traffic network or CABs placed in the traffic network; communicating, by the remotely located computing environment, a form factor control to a CAB in response to the traffic information; and adjusting a form factor of the CAB in response to the form factor control.

Abstract: A security system for vetting run-time operation of device hardware. A model stores vetted states based on device hardware security signals, a severity level value and at least one vetted next state. The vetting system compares each state of the device hardware with the vetted next states of a current state, and provides an indication and a severity level when the real next state does not match a vetted next state. In response to the indication, the synchronization system performs synchronization by comparing each subsequent real next state of the device hardware with the vetted states until initial synchronization occurs when any subsequent real next state matches a vetted state. The learning system receives feedback from the device hardware in response to the indication, and when indicated by the feedback, updates the model in accordance with the feedback.

Abstract: Various examples are provided related to multi-purpose context-aware bumps (CABs) that can support dynamic adaptation of form factors and functionality. In one example, a CAB system can include sensors distributed in a traffic network and communicatively coupled to a remotely located computing environment; context-aware bumps (CABs) placed in the traffic network and communicatively coupled to the remotely located computing environment; and a CAB application configured to adjust a form factor of a CAB in response to information obtained from the sensors and/or CABs. In another example, a method can include receiving, by a remotely located computing environment, traffic information from sensors distributed in a traffic network or CABs placed in the traffic network; communicating, by the remotely located computing environment, a form factor control to a CAB in response to the traffic information; and adjusting a form factor of the CAB in response to the form factor control.

Abstract: A security system for vetting run-time operation of device hardware. A model stores vetted states based on device hardware security signals, a severity level value and at least one vetted next state. The vetting system compares each state of the device hardware with the vetted next states of a current state, and provides an indication and a severity level when the real next state does not match a vetted next state. In response to the indication, the synchronization system performs synchronization by comparing each subsequent real next state of the device hardware with the vetted states until initial synchronization occurs when any subsequent real next state matches a vetted state. The learning system receives feedback from the device hardware in response to the indication, and when indicated by the feedback, updates the model in accordance with the feedback.

Abstract: One or more non-transitory computer-readable storage media is provided, the storage media is configured to store instructions that, when executed by a processor included in an apparatus, cause the processor to perform operations comprising: identify a plurality of transition faults that is to possibly occur in a circuit; generate a plurality of modified fault expressions, at least one of the plurality of modified fault expressions being associated with a corresponding transition fault of the plurality of transition faults; identify a plurality of test patterns, wherein at least one test pattern of the plurality of test patterns results in satisfiability of corresponding one or more of the plurality of modified fault expressions; and output the plurality of test patterns to a testing arrangement to test the circuit

Abstract: A method is described that includes performing the following by executing program code on a computing system. Generating an expression describing the operation of an electronic circuit for each of a plurality of faults within the circuit. Generating a plurality of fault equations for each of the faults that compare output bits of a faulty circuit with output bits of a working circuit. Combining the fault equations into a conjunctive logical expression. Attempting to solve a problem posed by the conjunctive logical expression with a MAXSAT solver to generate a test vector for the electronic circuit.

Abstract: The inventors have discovered a collection of proteinaceous biomarkers (“AD biomarkers) which can be measured in peripheral biological fluid samples to aid in the diagnosis of neurodegenerative disorders, particularly Alzheimer's disease and mild cognitive impairment (MCI). The invention further provides methods of identifying candidate agents for the treatment of Alzheimer's disease by testing prospective agents for activity in modulating AD biomarker levels.

Abstract: The inventors have discovered a collection of proteinaceous biomarkers (“AD biomarkers) which can be measured in peripheral biological fluid samples to aid in the diagnosis of neurodegenerative disorders, particularly Alzheimer's disease and mild cognitive impairment (MCI). The invention further provides methods of identifying candidate agents for the treatment of Alzheimer's disease by testing prospective agents for activity in modulating AD biomarker levels.

Abstract: The inventors have discovered sets of proteinaceous biomarkers (“AD biomarkers”) which can be measured in peripheral biological fluid samples to aid in the diagnosis of neurodegenerative disorders, particularly Alzheimer's disease. The invention further provides methods of identifying candidate agents for the treatment of Alzheimer's disease by testing prospective agents for activity in modulating the levels of the AD biomarkers.

Abstract: The inventors have discovered a collection of proteinaceous biomarkers (“AD biomarkers) which can be measured in peripheral biological fluid samples to aid in the diagnosis of neurodegenerative disorders, particularly Alzheimer's disease and mild cognitive impairment (MCI). The invention further provides methods of identifying candidate agents for the treatment of Alzheimer's disease by testing prospective agents for activity in modulating AD biomarker levels.