Patents by Inventor Sandipan Ghosh

Sandipan Ghosh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11790147
    Abstract: Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic design library including a plurality of design rules. Embodiments may include generating a routing graph, based upon, at least in part, the plurality of design rules, wherein the routing graph is a virtual representation of all of the available routing space for all routing layers associated with an electronic design. Embodiments may further include dynamically updating the routing graph at a graphical user interface, based upon, at least in part, a creation of a routing segment or a via at the graphical user interface.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: October 17, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hongzhou Liu, Rahaprian Premavathi Mudiarasan, Sandipan Ghosh, Hui Xu, Chris (Shyh-Chang) Lin, Joshua Baudhuin, Ron Pyke, Juno Lin, Allen You, Yu Liu, Jiulong Zhang, Thomas Richards
  • Patent number: 10769346
    Abstract: Disclosed is an approach for implementing placement for an electronic design, where when a dragged object is moved into a desired area, existing objects in that location are automatically moved as necessary in correspondence to the movement of the dragged object. Existing objects are only moved if they are causing a spacing violation or overlap with the dragged object being moved, either directly or indirectly.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 8, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Yu, Hui Xu, Karun Sharma, Sandipan Ghosh
  • Patent number: 10733351
    Abstract: Embodiments according to the present disclosure relate to physically implementing an integrated circuit design while conforming to the requirements of complex color based track systems, and using information about instances that have been included in the design. In particular, the present embodiments allow for the automatic creation of WSPs by examining heights and placement orientations of instances, along with the width, spacing, and colors of instance pins and blockages. In these and other embodiments, techniques are provided for filling gaps between generated tracks, as well as for generating tracks to account for the possibility of flipped or mirrored instances.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: August 4, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Gary Matsunami, Karun Sharma, Sandipan Ghosh, Yinnie Lee
  • Patent number: 9305133
    Abstract: A system and method are provided for selective application and expeditious reconciliation of constraints within a hierarchy of circuit design constraints. A semi-transparent constraint editor user interface is provided in contextual registration near detected violations during editing interactions with a circuit design. The constraint editor provides a simplified representation of a lookup order of a hierarchy of constraints applicable to an object related to the detected violation. The user is then able to easily modify constrained values within the lookup order, modify the lookup order, or modify the editing interaction to reconcile the violation expeditiously all while maintaining context within the circuit design.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: April 5, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sandipan Ghosh, Anjna Khanna
  • Patent number: 8612923
    Abstract: Methods, systems, computer program products for editing electrical circuits that facilitate and speed the layout of electrical circuits. Embodiments provide high-altitude editing capabilities to the user that enable the user to more easily select circuit items in congested layouts and schematic diagrams, and modify and arrange circuit items with respect to one another in congested layouts and schematic diagrams. Additional embodiments are directed to enabling EDA commands and the like to have context sensitivity, neighborhood awareness, and/or an ability to anticipate intentions of the user.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: December 17, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Rajan Arora, Chayan Majumder, Sandipan Ghosh, Anil Kumar Arya
  • Patent number: 8327315
    Abstract: According to various embodiments of the invention, a system and method for editing process rules for circuit design through a graphical editor is provided. In some embodiments, the graphical editor is a circuit design tool that provides the user of the tool, such as a circuit designer or process engineer, the ability to visualize, modify, create, or remove process rules through a graphical user interface (“GUI”). These process rules, also known as constraints or circuit design constraints, relate to the layout of circuits and is grouped into constraint groups (also known as “circuit design constraint groups”) that can be associated to specific circuit design objects.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: December 4, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sandipan Ghosh, Hitesh Marwah, Pawan Fangaria, Arbind Kumar
  • Patent number: 8271909
    Abstract: Embodiments of the invention provide system and methods for EDA tools. Specifically, some embodiments of the invention provide an input infrastructure for EDA tools that gathers pertinent information surrounding an input cursor's present locality (or neighborhood) and then analyzes the pertinent information in view of an issued command to automatically determine suitable targets or subsequent operations that a user of the EDA tool may want to select next.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: September 18, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chayan Majumder, Sandipan Ghosh, Anil Kumar Arya, Pawan Kumar Fangaria, Rajan Arora
  • Publication number: 20100205576
    Abstract: Embodiments of the invention provide system and methods for EDA tools. Specifically, some embodiments of the invention provide an input infrastructure for EDA tools that gathers pertinent information surrounding an input cursor's present locality (or neighborhood) and then analyzes the pertinent information in view of an issued command to automatically determine suitable targets or subsequent operations that a user of the EDA tool may want to select next.
    Type: Application
    Filed: February 6, 2009
    Publication date: August 12, 2010
    Inventors: CHAYAN MAJUMDER, Sandipan Ghosh, Anil Kumar Arya, Pawan Kumar Fangaria
  • Publication number: 20100205575
    Abstract: Disclosed are methods, systems, computer program products for editing electrical circuits that facilitate and speed the layout of electrical circuits. Embodiments disclosed herein provide high-altitude editing capabilities to the user that enable the user to more easily select circuit items in congested layouts and schematic diagrams, and modify and arrange circuit items with respect to one another in congested layouts and schematic diagrams. Additional embodiments disclosed herein are directed to enabling EDA commands and the like to have context sensitivity, neighborhood awareness, and/or an ability to anticipate intentions of the user.
    Type: Application
    Filed: June 22, 2009
    Publication date: August 12, 2010
    Applicant: Cadence Design Systems, Inc.
    Inventors: Rajan Arora, Chayan Majumder, Sandipan Ghosh, Anil Kumar Arya