Abstract: An image pixel may include a shutter element that is operable in an open state during which a corresponding photodiode accumulates charge and a closed state during which charge is drained from the photodiode. During a first portion of an image frame, the image pixel may operate in a flicker mitigation mode in which a non-continuous exposure period is used. During a second portion of the image frame, the image pixel may operate in a high dynamic range mode in which images are obtained with exposures of varying lengths. To conserve memory requirements, the signal from the flicker mitigation mode may not be sampled until the end of the first exposure of the high dynamic range mode.

Abstract: An image pixel may include a shutter element that is operable in an open state during which a corresponding photodiode accumulates charge and a closed state during which charge is drained from the photodiode. During a first portion of an image frame, the image pixel may operate in a flicker mitigation mode in which a non-continuous exposure period is used. During a second portion of the image frame, the image pixel may operate in a high dynamic range mode in which images are obtained with exposures of varying lengths. To conserve memory requirements, the signal from the flicker mitigation mode may not be sampled until the end of the first exposure of the high dynamic range mode.

Abstract: An image pixel may include a shutter element that is operable in an open state during which a corresponding photodiode accumulates charge and a closed state during which charge is drained from the photodiode. During a first portion of an image frame, the image pixel may operate in a flicker mitigation mode in which a non-continuous exposure period is used. During a second portion of the image frame, the image pixel may operate in a high dynamic range mode in which images are obtained with exposures of varying lengths. To conserve memory requirements, the signal from the flicker mitigation mode may not be sampled until the end of the first exposure of the high dynamic range mode.

Abstract: An image pixel may include a shutter element that is operable in an open state during which a corresponding photodiode accumulates charge and a closed state during which charge is drained from the photodiode. During a first portion of an image frame, the image pixel may operate in a flicker mitigation mode in which a non-continuous exposure period is used. During a second portion of the image frame, the image pixel may operate in a high dynamic range mode in which images are obtained with exposures of varying lengths. To conserve memory requirements, the signal from the flicker mitigation mode may not be sampled until the end of the first exposure of the high dynamic range mode.

Abstract: An imaging system may include a rolling shutter image sensor, data rate reduction circuitry, and image processing circuitry. The image sensor may output image data to the data rate reduction circuitry at a first high speed data rate. The data rate reduction circuitry may store the image data at the first data rate and may output the stored image data at a second reduced speed data rate. The image processing circuitry may receive the image data at the second data rate and may perform image processing operations at the second data rate. The data rate reduction circuitry may generate accumulated image frames by accumulating image frames received from the image sensor at the first data rate and may provide the accumulated frames to the image processing circuitry at the second data rate. The image processing circuitry may perform image processing operations on the accumulated frames at the second data rate.

Abstract: An image sensor with an array of image sensor pixels is provided. Each image sensor pixel may include a set of photodiodes formed in a semiconductor substrate, a color filter structure formed over the set of photodiodes, a microlens formed over the color filter structure, and associated pixel circuitry coupled to the set of photodiodes. The set of photodiodes may include at least two photodiodes linked together via a preferential blooming channel that provides a reduced potential barrier between the two photodiodes. This allows excess charge to spill over from one photodiode to another when more charge is concentrated in a particular photodiode. Configured in this way, the pixel can provide depth sensing capabilities without suffering from reduced pixel capacity.

Abstract: An image sensor with an array of image sensor pixels is provided. Each image sensor pixel may include a set of photodiodes formed in a semiconductor substrate, a color filter structure formed over the set of photodiodes, a microlens formed over the color filter structure, and associated pixel circuitry coupled to the set of photodiodes. The set of photodiodes may include at least two photodiodes linked together via a preferential blooming channel that provides a reduced potential barrier between the two photodiodes. This allows excess charge to spill over from one photodiode to another when more charge is concentrated in a particular photodiode. Configured in this way, the pixel can provide depth sensing capabilities without suffering from reduced pixel capacity.

Abstract: An imaging system may include a rolling shutter image sensor, data rate reduction circuitry, and image processing circuitry. The image sensor may output image data to the data rate reduction circuitry at a first high speed data rate. The data rate reduction circuitry may store the image data at the first data rate and may output the stored image data at a second reduced speed data rate. The image processing circuitry may receive the image data at the second data rate and may perform image processing operations at the second data rate. The data rate reduction circuitry may generate accumulated image frames by accumulating image frames received from the image sensor at the first data rate and may provide the accumulated frames to the image processing circuitry at the second data rate. The image processing circuitry may perform image processing operations on the accumulated frames at the second data rate.

Abstract: A system of taking images of different sensitivities at the same time uses both an image sensor, and an auxiliary part to the image sensor. The image sensor element can be a photogate, and the auxiliary part can be the floating diffusion associated with the photogate. Both the photogate and the floating diffusion accumulate charge. Both are sampled at different times. The floating diffusion provides a lower sensitivity amount of charge than the photogate itself. The system can have a photogate and floating diffusion in each pixel along with a select transistor, a reset transistor, and a follower transistor. All of this circuitry can be formed of CMOS for example. The system can also operate in a column/parallel mode, where each column of the photo sensor array can have a column signal processor which samples and holds the reset signal, the floating diffusion signal and the photogate signal.

Abstract: A system of taking images of different sensitivities at the same time uses both an image sensor, and an auxiliary part to the image sensor. The image sensor element can be a photogate, and the auxiliary part can be the floating diffusion associated with the photogate. Both the photogate and the floating diffusion accumulate charge. Both are sampled at different times. The floating diffusion provides a lower sensitivity amount of charge than the photogate itself. The system can have a photogate and floating diffusion in each pixel along with a select transistor, a reset transistor, and a follower transistor. All of this circuitry can be formed of CMOS for example. The system can also operate in a column/parallel mode, where each column of the photo sensor array can have a column signal processor which samples and holds the reset signal, the floating diffusion signal and the photogate signal.

Abstract: A system of taking images of different sensitivities at the same time uses both an image sensor, and an auxiliary part to the image sensor. The image sensor element can be a photogate, and the auxiliary part can be the floating diffusion associated with the photogate. Both the photogate and the floating diffusion accumulate charge. Both are sampled at different times. The floating diffusion provides a lower sensitivity amount of charge than the photogate itself. The system can have a photogate and floating diffusion in each pixel along with a select transistor, a reset transistor, and a follower transistor. All of this circuitry can be formed of CMOS for example. The system can also operate in a column/parallel mode, where each column of the photo sensor array can have a column signal processor which samples and holds the reset signal, the floating diffusion signal and the photogate signal.

Abstract: A CMOS imager includes an array of active pixel sensors, wherein each pixel is associated with a respective column in the array. The imager also includes multiple circuits for reading out values of pixels from the active sensor array. Each readout circuit can be associated with a respective pair of columns in the array and can include first and second sample-and-hold circuits. The first and second sample-and-hold circuits are associated, respectively, with first and second columns of pixels in the array. Each readout circuit also includes an operational amplifier-based charge sensing circuit that selectively provides an amplified differential output signal based on signals sampled either by the first sample-and-hold circuit or the second sample-and-hold circuit. The readout circuit also has an analog-to-digital converter for converting the differential output to a corresponding digital signal using a successive approximation technique.

Abstract: The present invention provides an improved column readout circuitry and method of operation which minimizes substrate and other common mode noise during a read out operation. The circuit improves the consistency of the pixel to pixel output of the pixel array and increases the dynamic range of the pixel output. This is accomplished by obtaining a differential readout of the reset signal and integrated charge signal from a desired pixel along with the reset signal and charge signal from a reference circuit. In this manner common mode noise can be minimized by a combination of signals from the desired and reference pixels in the sample and hold aspect of the column circuitry. In one exemplary embodiment of the invention, a 3T pixel arrangement is used. In another exemplary embodiment, a 4T arrangement is used. Additional exemplary embodiments provide differential column readout circuitry that can be used with any two signal sources.

Abstract: A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry, before the amplifier configuration of the stages/channels is switched. The discharging act occurs when a short reset pulse is generated between two clock phases. The short reset pulse is applied to a switch connected to the operational amplifier input. When the reset pulse closes the switch, a discharge path is created and any parasitic capacitance at the operational amplifier input is discharged through the path. The discharging of the parasitic capacitance substantially mitigates the memory effect and the problems associated with the memory effect.

Abstract: Charge is integrated in N>=2 different groups within a frame buffer to form multiple image fields.

Abstract: An apparatus such as an imager includes groups of sensors each of which includes subgroups of sensors. Subgroup select circuits are coupled to outputs from respective subgroups of sensors, and group select circuits are coupled to outputs from subgroup select circuits associated with respective ones of the groups. A bus is coupled to receive outputs from the group select circuits. A controller can provide control signals to the subgroup select circuits and the group select circuits to selectively enable the respective subgroup select circuits and group select circuits to pass signals from the sensors to the bus one sensor at a time.

Abstract: A system of reducing power consumption in and active pixels sensor. The sensor is broken into different blocks, and each of the blocks is individually optimized. The optimization may include minimizing the parasitic capacitance on the readout bus, turning off biases when not in use, and operating in a way that minimizes static power consumption of different elements such as A/D converters.

Abstract: The present invention provides an improved column readout circuitry and method of operation which minimizes substrate and other common mode noise during a read out operation. The circuit improves the consistency of the pixel to pixel output of the pixel array and increases the dynamic range of the pixel output. This is accomplished by obtaining a differential readout of the reset signal and integrated charge signal from a desired pixel along with the reset signal and charge signal from a reference circuit. In this manner common mode noise can be minimized by a combination of signals from the desired and reference pixels in the sample and hold aspect of the column circuitry. In one exemplary embodiment of the invention, a 3T pixel arrangement is used. In another exemplary embodiment, a 4T arrangement is used. Additional exemplary embodiments provide differential column readout circuitry that can be used with any two signal sources.

Abstract: An imaging circuit using an asymmetric comparator to detect an oversaturated pixel is disclosed. The comparator employs a transistor differential pair which are fabricated to be slightly unbalanced. By varying the channel widths of the two transistors during fabrication, the voltage required to trigger the comparator can be raised or lowered as desired to set an oversaturation level which triggers the comparator.

Abstract: A row driver circuit is disclosed for supplying a reset voltage to a plurality of reset transistors of an active pixel sensor array while minimizing gate induced drain leakage (GIDL). The row driver circuit is configured to supply a high voltage level (e.g., Vdd or higher) to the reset transistors of the array during a reset operation. The row driver circuit is further configured to supply a low voltage level (e.g., a voltage level higher than ground) to the reset transistors of the array when the pixels are not being reset (e.g., during integration). The reduced potential difference realized between the respective gates of the reset transistors and the respective photodiodes of the pixels, when the pixels are not being reset, results in reduced GIDL.