Abstract: A processing device includes a transmitter, a difference amplifier, and a data detector. A first output buffer of the transmitter receives data and has a first output coupled to a channel that is designed to have a first impedance value, but that has a second impedance value that which may or may not be equal to the first impedance value. A second output buffer of the transmitter receives the data and has an output coupled to a circuit that has the first impedance. The difference amplifier has inputs coupled to the outputs of the first and second output buffers. The data detector is coupled to an output of the difference amplifier. The data processing device operates in a test operation mode to provide test data to the first and second output buffers and to determine whether the second impedance is equal to the first impedance based on information from the data detector.

Abstract: In one or more embodiments, a coupon with a plurality of cutouts based on a chirp waveform may be used to align a drilling machine to a PCB. Light may be passed through the coupon and a camera may capture the light. A processor may perform zero padding, calculate a two-dimensional (2D) fast Fourier transform (FFT) of the image, multiply by a pre-calculated complex conjugate 2D FFT of the coupon, then calculate a cross correlation based on an inverse 2D FFT. Embodiments may find the best fitting coordinates of the peaks and use the coordinate as a correction factor for referencing a drilling machine to ensure drills are centered and/or aligned relative to power plane pads or antipads.

Abstract: In one or more embodiments, a system and method for impedance matching across subassemblies comprises forming a PCB with wider traces, wherein a trace is formed based on a width corresponding to a trace design and a tolerance. The larger width reduces a reflection coefficient to reduce impedance differences. A Surface mount technology (SMT) breakout area may include a thicker microstrip and a conductive silk screen layer may be added to further improve impedance matching without increasing the total height of a PCB.

Abstract: A connection assembly including a receptacle connector having a first and a second end, including: a shell, including a first outer surface and a second outer surface; a shield surrounding the shell, the shield including: a first portion including a first cam flange, the first portion rotatable about a first spring hinge; a second portion including a second cam flange, the second portion rotatable about a second spring hinge; a mating connector removable coupleable to the receptacle connector, including: an adjustment member, wherein, when a positioning of the adjustment member is adjusted to decrease a distance between the adjustment member and the second end of the receptacle connector, the adjustment member adjusts a distance between the first cam flange and the second cam flange to rotate the first portion of the shield about the first spring hinge and rotate the second portion of the shield about the second spring hinge.

Abstract: A circuit includes an inductive circuit trace and a nonlinear device. The circuit conducts a signal input to a load. The circuit trace receives the signal input at a first end of the circuit trace and provides the signal input to the load at a second end of the circuit trace. The nonlinear device is coupled at the second end and is configured to increase a voltage rise time of the signal input.

Abstract: A printed circuit board includes a dielectric and a connector. The connector is mounted on the dielectric. The connector includes a first connector lead, a first contact point, and a first connector wipe. The first connector wipe includes a plurality of low impedance bumps. The low impedance bumps create an impedance mismatch between the first connector lead and the first connector wipe.

Abstract: A printed circuit board includes a dielectric material, a signal trace on a surface of the dielectric material, a signal layer within the dielectric material, a via including plating, and multiple back drill locations. The plating provides an electrical communication between the signal trace and the signal layer, and the via has a diameter. The back drill locations are along a length of the via beyond the signal layer. A first combined diameter of the back drill locations at a bottom of the back drill locations is equal to the dimeter of the via. A second combined diameter of the back drill locations at a top of the back drill locations is greater than the dimeter of the via.

Abstract: A printed circuit board includes a dielectric and a connector. The dielectric has a first dielectric constant. A first area within the dielectric has a second dielectric constant. The connector is mounted on the dielectric. The connector includes a first connector lead mounted on the dielectric, a first contact point above the dielectric, and a first connector wipe. The first connector wipe is disposed above the first area.

Abstract: A printed circuit board includes a dielectric and a connector. The connector is mounted on the dielectric. The connector includes a first connector lead, a first contact point, and a first connector wipe. The first connector wipe includes a first wider section adjacent to the first contact point. The first wider section creates an impedance mismatch between the first connector lead and the first connector wipe.

Abstract: A CPU includes a processor die and a substrate. The processor die includes first signal contacts, power contacts, and ground contacts. The processor die is affixed and electrically coupled to the substrate on a first surface of the substrate. The substrate routes the first signal contacts to associated second signal contacts on a second surface of the substrate. The substrate further routes a subset of the power contacts to a power pad on the first surface of the substrate, and routes a subset of the ground contacts to a ground pad on the first surface of the substrate.

Abstract: A printed circuit board comprising a first connection pad coupled to a first portion of a microstrip trace and a second connection pad coupled to a second portion of the microstrip trace. The microstrip trace has a first impedance along the first portion and a second impedance along the second portion. The printed circuit board also includes a conductive plane on a top surface of the microstrip trace, wherein the conductive plane includes a plurality of cutouts to reduce impedance mismatch between the first impedance and the second impedance.

Abstract: A printed circuit board comprising a primary dielectric layer disposed underneath a microstrip trace and a secondary dielectric layer disposed above portions of the primary dielectric layer and the microstrip trace. The printed circuit board also includes a conductive plane disposed above the secondary dielectric layer and the microstrip trace, wherein the conductive plane is grounded.

Abstract: A receiver for a high-speed data communication interface includes a differential data signal input, a first termination resistor, a second termination resistor, and a noise measurement node. The differential data signal input includes a positive signal input and a negative signal input. The first termination resistor terminates the positive signal input to a reference voltage node. The second termination resistor terminates the negative signal input to the reference voltage node. The noise measurement node is coupled to detect common mode noise at the reference voltage node.

Abstract: An integrated circuit device includes a multiplexor and multiple receivers for high-speed data communication interfaces. The multiplexor includes multiple signal inputs, a selector input, and a signal output. Each receiver includes a differential data signal input including a positive signal input and a negative signal input, a first termination resistor to terminate the positive signal input to a reference voltage node, a second termination resistor to terminate the negative signal input to the reference voltage node, and a noise measurement node to detect common mode noise at the reference voltage node, the noise measurement node coupled to an associated one of the signal inputs.

Abstract: A test system is provided for determining that data channels on a printed circuit board (PCB) have a predetermined impedance level. Each channel in the PCB is terminated at the predetermined impedance level. The PCB has a receptacle for coupling a device to the channels. An instrument can be installed into the receptacle, and includes connections to each of the channels, and a connector that is coupled to the connections by a channel splitter network. A test device is coupled to the connector and provides a test signal to the connector, receives a return signal from the connector, and determines that at least one of the channels does not have the predetermined impedance based upon the return signal.

Abstract: An information handling system includes a PCB, a transmitter for a data communication interface, a receiver for the data communication interface, a first channel instantiated in the printed circuit board, and a second channel instantiated in the printed circuit board. The receiver includes a first input and a second input. The first channel is coupled between an output of the transmitter and the first input of the receiver and is routed in a first path in the printed circuit board. The second channel is coupled to provide a reference voltage to the second input of the receiver and is routed in a second path in the printed circuit board. At least a portion of the second path is routed adjacent to a portion of the first path.

Abstract: A cable comprising a conductor in a center of the cable, a dielectric layer surrounding the conductor and a resistive coating may be provided. The resistive coating may be applied to an exposed portion of the conductor and disposed with the dielectric layer. The resistance of the resistive coating when combined with an impedance of the cable prior to application of the resistive coating reaches a target impedance.

Abstract: A printed circuit board of an information handling system includes a pair of signal vias including a pair of keepout objects. Each one of the keepout objects surrounds one of the signal vias. The printed circuit board includes a pair of signal traces that includes a positive signal trace and a negative signal trace, wherein the pair of signal traces are between the keepout objects, and wherein a width of each of the signal traces is increased.

Abstract: An information handling system includes a PCB, a CPU, a power distribution hat, and a heat sink. The PCB includes a first power contact on a first surface of the PCB and a first ground contact on a second surface of the PCB. The CPU includes a substrate and is affixed and electrically coupled to the first surface of the PCB by a first surface of the substrate. A second surface of the substrate includes a second power contact and a second ground contact. The power distribution hat couples the first power contact with the second power contact. The heat sink couples the first ground contact with the second ground contact.

Abstract: An information handling system includes a PCB, a CPU, a power distribution hat, and a heat sink. The PCB includes a first power contact on a first surface of the PCB and a first ground contact on a second surface of the PCB. The CPU includes a substrate and is affixed and electrically coupled to the first surface of the PCB by a first surface of the substrate. A second surface of the substrate includes a second power contact and a second ground contact. The power distribution hat couples the first power contact with the second power contact. The heat sink couples the first ground contact with the second ground contact.