Patents by Inventor Sandra J. Jackson

Sandra J. Jackson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and systems for synchronization between multiple clock domains
    Patent number: 10355851
    Abstract: A synchronization solution is described, which, in one aspect, allowed finer grained segmentation of clock domains on a chip. This solution incorporates computation into the synchronization overhead time and is called Gradual Synchronization. With Gradual Synchronization as a synchronization method, the design space of a chip could easily mix both asynchronous and synchronous blocks of logic, paving the way for wider use of asynchronous logic design.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: July 16, 2019
    Assignee: Cornell University
    Inventors: Rajit Manohar, Sandra J. Jackson
  • METHODS AND SYSTEMS FOR SYNCHRONIZATION BETWEEN MULTIPLE CLOCK DOMAINS
    Publication number: 20190007190
    Abstract: A synchronization solution is described, which, in one aspect, allowed finer grained segmentation of clock domains on a chip. This solution incorporates computation into the synchronization overhead time and is called Gradual Synchronization. With Gradual Synchronization as a synchronization method, the design space of a chip could easily mix both asynchronous and synchronous blocks of logic, paving the way for wider use of asynchronous logic design.
    Type: Application
    Filed: May 29, 2018
    Publication date: January 3, 2019
    Inventors: Rajit Manohar, Sandra J. Jackson
  • Methods and systems for synchronization between multiple clock domains
    Patent number: 9985774
    Abstract: A synchronization solution is described, which, in one aspect, allowed finer grained segmentation of clock domains on a chip. This solution incorporates computation into the synchronization overhead time and is called Gradual Synchronization. With Gradual Synchronization as a synchronization method, the design space of a chip could easily mix both asynchronous and synchronous blocks of logic, paving the way for wider use of asynchronous logic design.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: May 29, 2018
    Assignee: Cornell University
    Inventors: Rajit Manohar, Sandra J. Jackson
  • METHODS AND SYSTEMS FOR SYNCHRONIZATION BETWEEN MULTIPLE CLOCK DOMAINS
    Publication number: 20170214514
    Abstract: A synchronization solution is described, which, in one aspect, allowed finer grained segmentation of clock domains on a chip. This solution incorporates computation into the synchronization overhead time and is called Gradual Synchronization. With Gradual Synchronization as a synchronization method, the design space of a chip could easily mix both asynchronous and synchronous blocks of logic, paving the way for wider use of asynchronous logic design.
    Type: Application
    Filed: April 6, 2017
    Publication date: July 27, 2017
    Inventors: Rajit Manohar, Sandra J. Jackson