Abstract: An intrusion detection mechanism is provided for flexible, automatic, thorough, and consistent security checking and vulnerability resolution in a heterogeneous environment. The mechanism may provide a predefined number of default intrusion analysis approaches, such as signature-based, anomaly-based, scan-based, and danger theory. The intrusion detection mechanism also allows a limitless number of intrusion analysis approaches to be added on the fly. Using an intrusion detection skin, the mechanism allows various weights to be assigned to specific intrusion analysis approaches. The mechanism may adjust these weights dynamically. The score ration can be tailored to determine if an intrusion occurred and adjusted dynamically. Also, multiple security policies for any type of computing element may be enforced.

Abstract: A memory coherence protocol is provided for using cache line access frequencies to dynamically switch from an invalidation protocol to an update protocol. A frequency access count (FAC) is associated with each line of data in a memory area, such as each cache line in a private cache corresponding to a CPU in a multiprocessor system. Each time the line is accessed, the FAC associated with the line is incremented. When the CPU, or process, receives an invalidate signal for a particular line, the CPU checks the FAC for the line. If the CPU, or process, determines that it is a frequent accessor of a particular line that has been modified by another CPU, or process, the CPU sends an update request in order to obtain the modified data. If the CPU is not a frequent accessor of a line that has been modified, the line is simply invalidated in the CPU's memory area.

Abstract: A system and method of improved handling of large pages in a virtual memory system. A data memory management unit (DMMU) detects sequential access of a first sub-page and a second sub-page out of a set of sub-pages that comprise a same large page. Then, the DMMU receives a request for the first sub-page and in response to such a request, the DMMU instructs a pre-fetch engine to pre-fetch at least the second sub-page if the number of detected sequential accesses equals or exceeds a predetermined value.

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC.

Abstract: A system, method, and computer program product for adaptively identifying unauthorized intrusions in a networked data processing system. In accordance with the method of the present invention, an intrusion detection module receives system event data that may be utilized for intrusion detection. The received system event data is processed utilizing multiple intrusion detection techniques including at least one behavior-based intrusion detection technique to generate an intrusion detection result. In response to the intrusion detection result indicating an unauthorized intrusion, at least one knowledge-based intrusion detection corpus is updated utilizing the system event data. In a preferred embodiment, the intrusion detection system/method is implemented in a network data processing environment in which the knowledge-based intrusion detection corpus is communicatively accessible by multiple elements coupled to the networked data processing system.

Abstract: A system, apparatus and method of adaptively queueing processes for execution scheduling are provided. When a process yields its processor to another process, it is generally placed in a queue before it is re-scheduled for execution. If it is re-scheduled for execution within a longer period of time than needed, the next time it has to be placed in a queue, it will be placed in a queue or at a location in a queue where it will be scheduled for execution in a shorter amount of time. If it is re-scheduled for execution within a period of time that is shorter than needed, the next time it has to be placed in a queue, it will be placed in a queue or at a location in a queue where it will be scheduled for execution within a longer period of time.

Abstract: Method, system and computer program product for managing resources in a data processing system. Knowledge provided by each subsystem of a plurality of subsystems of an operating system regarding behavior of the subsystem is shared by other subsystems of the operating system, and the shared knowledge, together with existing functional characteristics of the subsystems is used by the operating system to more efficiently manage resources in the data processing system.

Abstract: A method is provided for scheduling threads in a multi-processor system. In a first structure thread ids are stored for threads associated with a context switch. Each thread id identifies one thread. In a second structure entries are stored for groups of contiguous cache lines. Each entry is arranged such that a thread id in the first structure is capable of being associated with at least one contiguous cache line in at least one group, the thread identified by the thread id having accessed the at least one contiguous cache line. Patterns are mined for in the entries to locate multiples of a same thread id that repeat for at least two groups. Threads identified by the located multiples of the same thread id are mapped to at least one native thread, and are scheduled on the same processor with other threads associated with the at least two groups.

Abstract: The pharmaceutical composition is useful for treating epithelial tumors in a subject and contains at least two antigens and a pharmaceutically acceptable carrier, where each of the antigens induces or is capable of inducing a cutaneous delayed type hypersensitivity (DTH) response in the subject. This composition is particularly useful in treating epithelial tumors, such as warts or verrucae, that are induced by or related to papillomavirus. Antigens useful in the present pharmaceutical composition are anergy panel antigens, such as killed mumps virus, candida extract, trichophyton extract or comparable antigenic extracts. An additional pharmaceutical composition, also useful for treating epithelial tumors, contains at least one antigen that induces or is capable of inducing a cutaneous DTH response in a subject, at least one cytokine or colony stimulating factor and a pharmaceutically acceptable carrier. Kits containing these pharmaceutical compositions are useful for this immunotherapy.

Abstract: A system and method of adaptively reconfiguring a pool of buffers are provided. The buffers are initially configured to a size (i.e., a current size). Each time data is placed in the buffers by an application program, it is determined whether the size of the data is greater than the current size of the buffers. If the size of the data is greater than the current size of the buffers, the buffers are reconfigured to the size of the data if the number of times data of that size is stored in the buffers is greater than a first threshold. If, however, the size of the data is smaller than the current size of the buffers, the buffers may be reconfigured to the size of the data if the number of times data of that size is stored in the buffers is smaller than a second threshold.

Abstract: Handy Handle, an adult cart handle cover designed for use with shopping carts, airport luggage carts and or rented strollers at amusement park facilities. Handy Handle a new and innovative cart handle cover designed to protect adults hands from germs and bacteria when shopping or traveling and coming into contact with dirty cart handles. Now for the first time, adults can feel confident pushing a cart and holding on to the cart handle bar by being protected from germs and bacteria with a Handy Handle cart cover. Adults of any age (young, old, with or without children) now have the chance to be protected from germs and bacteria that have been proven by University researchers to be contaminated with serious live bacteria that can make us sick. Made from a durable, high quality cotton and or polyester material that is 100% machine washable and some material even contains CRF REPELLAN® finish that further protects against exposure to germs, bacteria and stains.

Abstract: An illuminated and decorative garage door cover assembly for use on an exterior surface of a garage door of the type having that contains an illuminated decorative display. The assembly can have a plurality of cover panels, each of which contains a portion of the display. The cover panels contain receptacles embedded therein that are electrically wired together. The receptacles receive lights that illuminate when power is applied to give an illuminated display. The display on the cover panels reflects holiday, seasonal, or other celebratory occasions. The display on the panels together when the garage door is in the closed position to form a composite display that is not colorful, but also illuminated to give greater appearance at night.

Abstract: A method is provided for scheduling threads in a multi-processor system. In a first structure thread ids are stored for threads associated with a context switch. Each thread id identifies one thread. In a second structure entries are stored for groups of contiguous cache lines. Each entry is arranged such that a thread id in the first structure is capable of being associated with at least one contiguous cache line in at least one group, the thread identified by the thread id having accessed the at least one contiguous cache line. Patterns are mined for in the entries to locate multiples of a same thread id that repeat for at least two groups. Threads identified by the located multiples of the same thread id are mapped to at least one native thread, and are scheduled on the same processor with other threads associated with the at least two groups.

Abstract: According to one aspect of the invention, there is provided a method for dynamically changing page types in a unified scalable shared-memory architecture. The method includes the step of assigning a default page type of a given page as simple cache only memory architecture (SCOMA). Upon n memory references, a first parameter of the given page is calculated. A second parameter of the given page is calculated, when the first parameter is greater than a first threshold. The page type of the given page is dynamically changed to cache-coherent non-uniform memory architecture (ccNUMA), when the second parameter is greater than a second threshold. The first and the second parameters are one of a page reference probability and one minus a page utilization, the second parameter being different than the first parameter. According to another aspect of the invention, the n memory references correspond to all pages.

Abstract: A method for assuring virtual atomic invalidation in a multilevel cache system wherein lower level cache locations store portions of a line stored at a higher level cache location. Upon receipt of an invalidation signal, the higher level cache location invalidates the line and places a HOLD bit on the invalidated line. Thereafter, the higher level cache sends invalidation signals to all lower level caches which store portions of the invalidated line. Each lower level cache invalidates its portion of the line and sets a HOLD bit on its portion of the line. The HOLD bits are reset after all line portion invalidations have been completed.

Abstract: A method of maintaining cache coherency in a shared memory multiprocessor system having a plurality of nodes, where each node itself is a shared memory multiprocessor. With this invention, an additional shared owner state is maintained so that if a cache at the highest level of cache memory in the system issues a read or write request to a cache line that misses the highest cache level of the system, then the owner of the cache line places the cache line on the bus interconnecting the highest level of cache memories.

Abstract: A method of reducing false sharing in a shared memory system by enabling two caches to modify the same line at the same time. More specifically, with this invention a lock associated with a segment of shared memory is acquired, where the segment will then be used exclusively by processor of the shared memory system that has acquired the lock. For each line of the segment, an invalidation request is sent to a number of caches of the system. When a cache receives the invalidation request, it invalidates each line of the segment that is in the cache. When each line of the segment is invalidated, an invalidation acknowledgement is sent to the global directory. For each line of the segment that has been updated or modified, the update data is written back to main memory. Then, an acquire signal is sent to the requesting processor which then has exclusive use of the segment.

Abstract: A mechanism to dynamically migrate a home node of a global page to a more suitable node for improving performance of parallel applications running on a S-COMA and other DSM systems. More specifically, consultation counts are maintained at each client node of a shared memory system, where the consultation count indicates the number of times the client node has consulted the dynamic for lines a page. This information is then used along with other information to decide on whether to change the dynamic home node to a more suitable node.

Abstract: A method for storing redundant information in an array of data storage devices such that data is protected against two simultaneous storage device failures. The method assigns each data block to two different parity sets, each protected by a different parity block. The protected data blocks and the parity block each reside on a different data storage device.

Abstract: A cache coherence protocol for a multiprocessor system. Each processor in the system has an associated cache capable of storing multiple word data lines. The system also includes a plurality of main memory modules, each having an associated distributed global directory storing directory information for lines stored in the associated main memory module. Each main memory module is connected to each processor by means of a multi-stage interconnection network. When a processor attempts to over-write an individual word in a line stored in its associated cache, a write request signal is sent to the appropriate global directory, and each other processor whose cache stores a copy of the line is notified of the request. When each other processor has responded with an acknowledgement, the first processor is allowed to proceed with the write.