Patents by Inventor Sandrine Nicolas

Sandrine Nicolas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250055492
    Abstract: In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.
    Type: Application
    Filed: October 28, 2024
    Publication date: February 13, 2025
    Inventors: Danika Perrin, Sandrine Nicolas
  • Patent number: 12155406
    Abstract: In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: November 26, 2024
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: Danika Perrin, Sandrine Nicolas
  • Publication number: 20230056937
    Abstract: In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.
    Type: Application
    Filed: August 5, 2022
    Publication date: February 23, 2023
    Inventors: Danika Perrin, Sandrine Nicolas
  • Publication number: 20230018356
    Abstract: In an embodiment an amplifier includes a first MOS transistor having a drain connected to an output of the amplifier and a source coupled to a first node configured to receive a first power supply potential, a first capacitive element connected between an input of the amplifier and a gate of the first MOS transistor, a first current source connecting the drain of the first MOS transistor to a second node configured to receive a second power supply potential and a resistive element and a second capacitive element connected in parallel between the gate and the drain of the first MOS transistor, the resistive element including a switched capacitor.
    Type: Application
    Filed: July 12, 2022
    Publication date: January 19, 2023
    Inventors: Hugo Gicquel, Sandrine Nicolas, Cedric Rechatin, Reiner Welk
  • Patent number: 10979063
    Abstract: An electronic circuit comprises capacitive structures that are connected to one or a plurality of nodes, where each of the capacitive structures is formed by a capacitor or by a plurality of capacitors electrically connected in parallel. The electronic circuit further comprises additional capacitors that are each connected to the one or plurality of nodes. For at least one distance between capacitors, the capacitive structures have a same average of values defined, for each capacitor of each capacitive structure, by the number of capacitors of the circuit connected to the one or plurality of nodes and located at the distance from the capacitor of the capacitive structure.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: April 13, 2021
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Sandrine Nicolas, Damien Giot, Serge Ramet, Reiner Welk
  • Publication number: 20200366308
    Abstract: An electronic circuit comprises capacitive structures that are connected to one or a plurality of nodes, where each of the capacitive structures is formed by a capacitor or by a plurality of capacitors electrically connected in parallel. The electronic circuit further comprises additional capacitors that are each connected to the one or plurality of nodes. For at least one distance between capacitors, the capacitive structures have a same average of values defined, for each capacitor of each capacitive structure, by the number of capacitors of the circuit connected to the one or plurality of nodes and located at the distance from the capacitor of the capacitive structure.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 19, 2020
    Inventors: Sandrine Nicolas, Damien Giot, Serge Ramet, Reiner Welk
  • Patent number: 10359800
    Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 23, 2019
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: Serge Ramet, Sandrine Nicolas, Danika Perrin, Cedric Rechatin
  • Patent number: 10063189
    Abstract: An amplification device includes an amplification stage having a transconductance amplification transistor and an output terminal. A biasing circuit is configured to bias in common mode the output terminal to a bias potential obtained on the basis of a voltage present between the gate and the source of the amplification transistor, and to compensate for parasitic variations of the voltage present between the gate and the source of the amplification transistor.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: August 28, 2018
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Michel Ayraud, Sandrine Nicolas
  • Publication number: 20180239384
    Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.
    Type: Application
    Filed: August 31, 2017
    Publication date: August 23, 2018
    Inventors: Serge Ramet, Sandrine Nicolas, Danika Perrin, Cedric Rechatin
  • Publication number: 20180152142
    Abstract: An amplification device includes an amplification stage having a transconductance amplification transistor and an output terminal. A biasing circuit is configured to bias in common mode the output terminal to a bias potential obtained on the basis of a voltage present between the gate and the source of the amplification transistor, and to compensate for parasitic variations of the voltage present between the gate and the source of the amplification transistor.
    Type: Application
    Filed: May 8, 2017
    Publication date: May 31, 2018
    Inventors: Michel Ayraud, Sandrine Nicolas
  • Patent number: 9013221
    Abstract: A receiver circuit for a differential input signal, may include a divider bridge having first and second ends, a midpoint therebetween, and intermediate points on either side of the midpoint. The divider bridge is coupled to receive the differential input signal at the first and second ends. A current generator is coupled to the divider bridge and configured to generate compensation currents associated respectively with components of the differential input signal. The divider bridge is configured to receive the compensation currents respectively at the intermediate points, and generate a compensated differential signal between the intermediate points.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Thierry Masson, Sandrine Nicolas, Colette Morche
  • Publication number: 20150077166
    Abstract: A receiver circuit for a differential input signal, may include a divider bridge having first and second ends, a midpoint therebetween, and intermediate points on either side of the midpoint. The divider bridge is coupled to receive the differential input signal at the first and second ends. A current generator is coupled to the divider bridge and configured to generate compensation currents associated respectively with components of the differential input signal. The divider bridge is configured to receive the compensation currents respectively at the intermediate points, and generate a compensated differential signal between the intermediate points.
    Type: Application
    Filed: September 8, 2014
    Publication date: March 19, 2015
    Inventors: Thierry Masson, Sandrine Nicolas, Colette Morche