Abstract: An active noise cancelling device including a sensor configured to convert acoustic signals into first audio signals and a speaker acoustically coupled to the sensor A control stage is configured to control the speaker based on the first audio signals to cause the speaker to produce cancelling acoustic waves that tend to suppress acoustic noise components in the acoustic signals. The control stage includes sigma-delta modulator digital filters.

Abstract: An active noise cancelling device including a sensor configured to convert acoustic signals into first audio signals and a speaker acoustically coupled to the sensor A control stage is configured to control the speaker based on the first audio signals to cause the speaker to produce cancelling acoustic waves that tend to suppress acoustic noise components in the acoustic signals. The control stage includes sigma-delta modulator digital filters.

Abstract: A digital circuit generates a phase synchronization signal for a digital input signal coded according to a biphase modulation. The phase synchronization signal is derived from a clock signal having a higher frequency than the maximum switching frequency of the digital input signal. The frequency of the clock signal is divided with a fully digital divider circuit having a non-integer ratio. The divider is self-synchronizing with the input digital signal. Control signals are used to enable or disable switching of the frequency divider. These control signals are generated by two circuits which sample the input signal with the master clock signal and analyze triplets of consecutive sampling values.

Abstract: A test signal with given spectral characteristics is injected at input to the quantizer stage of the converter. The same test signal is subjected to cross-correlation with a given signal so as to generate coefficients used for filtering the quantization noise converted into digital form. In this way, a compensation signal is obtained that is applied to the output signal of the quantizer stage jointly with a first compensation signal obtained by applying, to the quantization noise converted into digital form, the same transfer function 28) of the converter. In this way a signal is obtained which, in addition to being used as the global output signal of the converter, is also used for the aforesaid operation of cross-correlation with the test signal.

Abstract: A sigma-delta modulator of second or higher order includes two or more integrating stages, and a comparator connected in cascade to the integration stages. A signal having a logic level +1 is generated when an input signal to the sigma-delta modulator is positive, and a signal having a logic value −1 is generated when the input signal is negative. Regardless of its absolute value, a feedback line includes a low-pass filter and an adder circuit for adding a feedback signal. The signal output by the last of the integrating stages is filtered by the low-pass filter. The sigma-delta modulator further includes a second comparator having an input connected in common to the input of the first comparator and an output connected to an input of the low-pass filter. The second comparator outputs a logic signal having a positive value when the input signal is positive, and outputs a logic signal having a negative value when the input signal is negative.

Abstract: The ratio y(n) of two digital values, respectively a(n) and b(n), representing the n.sup.th elements of two respective sequences of digital input data representing two quantities slowly varying in time, is obtained by computingy(n)=y(n-1)+g*[a(n)-b(n)*y(n-1)]wherein g represents a multiplying factor. Within the domain of the z transform, the expression becomes:Y(z)=z.sup.-1 *Y(z)+g[A(z)-B(z)conv Y(z)*z.sup.-1where conv indicates an operation of convolution and which, for input sequences corresponding to signals filtered through a lowpass filter with a time constant greater than or equal to 3 msec is simplified to: ##EQU1## The approximation is exceptionally good and computation thereof may be achieved by the use of relatively simple hardware, without severely burdening the workload of a microprocessor.

Abstract: Generation of symmetrical temperature compensated reference voltages in mixed type integrated circuits (digital and analog) having a superior PSRR is provided. Such a circuit includes a voltage-to-current conversion stage of a temperature independent bandgap voltage for producing a differential pair of currents that are applied as inputs to a pair of resistor feedback operational amplifiers. The feedback resistors are integrated in an interlaced form with a resistor employed in the conversion stage so that they have the same thermal gradient. Output of the operational amplifiers provides two temperature compensated low noise symmetrical reference voltages.

Abstract: A microphone device having input terminals for receiving an input analog signal and output terminals to produce an output digital signal. The microphone device includes a converter circuit having input terminals coupled to the input terminals of the microphone device and an output terminal coupled to the output terminals of the microphone and an output terminal coupled to the output terminals of the microphone device.

Abstract: A method of injecting a whitening random signal in a Sigma Delta modulator with a high-pass transfer function of a quantization noise filter of a certain order, for converting a digital audio signal sampled at a certain clock frequency into an analog signal, comprises the steps of generating a flat-spectrum dither signal, filtering the dither signal with a high-pass transfer function of an order higher than the order of the transfer function of the Sigma Delta modulator, and summing the filtered signal to the sampled digital audio signal, quantized by the modulator. The method prevents the occurrence of disturbances that would otherwise occur as a result of intermodulation of subtle colorations observable in the vicinity of the Nyquist frequency. The disclosed hardware implementation of the method adds little to the hardware complexity.