Abstract: A Buck converter includes: a first power switch coupled between a supply voltage node and a switching node, where the first power switch is configure to be controlled by a first control signal; a boot-strap capacitor, where a first terminal of the boot-strap capacitor is coupled to the switching node; a first buffer coupled between a first node and a control terminal of the first power switch; a first switch circuit coupled between the first node and a second terminal of the boot-strap capacitor, where the first switch circuit is controlled by the first control signal, and is configured to pass through a first charging current provided by the boot-strap capacitor when the first control signal is asserted; and a slew-rate control capacitor, where a first terminal of the slew-rate control capacitor is coupled to the first node.

Abstract: A driving circuit is provided for switching a switching circuit which has a high-side switch circuit and a low-side switch circuit and a phase node between the high-side switch circuit and the low-side switch circuit. The driving circuit has: a driving voltage regulator with a driving node which provides a driving voltage; a high-side driver which has a supply node configured to be coupled to a bootstrap node of a bootstrap capacitance and to control a switching of the high-side switch circuit; and a low-side driver which has a supply node coupled to the driving node and configured to control a switching of the low-side switch circuit. Furthermore, the driving circuit has a circuitry configured to regulate the coupling between the driving node of the driving voltage regulator and the supply node of the high-side driver.

Abstract: During an amplifier calibration phase, input nodes are coupled to receive a common calibration voltage level, an adjustment signal is iteratively varied based on a programmable code, a calibration amplifier output is generated for each iteration of the adjustment signal, and successive calibration amplifier outputs are compared and checked for having different polarities. A value of the programmable code is stored based on the check. During an amplifier operating phase: the adjustment signal is generated based on the stored value and applied to the amplifier, and an input signal is applied to the input nodes, with the amplifier generating an output signal that is exempt from amplifier offset.

Abstract: A DC/DC converter including a low side and a high side is disclosed. The converter includes a first switching device being part of the low side, a low side current generator configured to generate a low side current flowing in the first switching device, a second switching device, a compensation resistor coupled in series to the second switching device, a valley current reference current generator configured to generate a valley current threshold current (Ivalclth) flowing in the second switching device and in the compensation resistor for obtaining a first voltage value, and a comparator configured to compare the first voltage value and a reference voltage for generating an error signal as a function of the comparison, the error signal controlling a conductivity of the first switching device of the low side.

Abstract: According to an embodiment, a bootstrap drive circuit for driving a bootstrap switch in a DC-DC converter is proposed. The bootstrap drive circuit includes a non-overlapping circuit, a first and a second capacitor, and a first and a second n-channel transistor. The non-overlapping circuit is configured to receive an input signal, the input signal being a function of a pulse width modulated (PWM) signal, wherein the input signal and the PWM signal are characterized by a first logic level, generate a first control signal from the input signal at a first output terminal of the non-overlapping circuit, the first control signal having the first logic level, and generate a second control signal from the input signal at a second output terminal of the non-overlapping circuit, the second control signal being characterized by a second logic level different from the first logic level.

Abstract: An integrated circuit device includes: one or more switches of a Buck converter; and a control circuit for the Buck converter including: a comparator configured to generate a comparator output signal by comparing a feedback voltage of the Buck converter with a compensation ramp voltage; a pulse generator configured to generate, in response to a rising edge in the comparator output signal, a pulse signal for controlling the Buck converter; a transconductance amplifier configured to generate, at an output terminal of the transconductance amplifier, a current proportional to a difference between a reference voltage and the feedback voltage; a capacitor coupled between the output terminal of the transconductance amplifier and a reference voltage node; and a ramp signal generator configured to generate the compensation ramp voltage by adding a voltage at the output terminal of the transconductance amplifier and a ramp voltage generated by the ramp signal generator.

Abstract: According to an embodiment, a circuit for transistor gate stress testing is proposed. The circuit includes a first p-channel MOSFET with its drain linked to the transistor's gate; a second p-channel MOSFET coupling its source to the first p-channel MOSFET's source at a node and its drain to a supply voltage; a first n-channel MOSFET with its source to ground and drain to the transistor's gate; a second n-channel MOSFET with its source to ground and drain to the second p-channel MOSFET's gate; a third p-channel MOSFET with its source and drain bridging the node to the second n-channel MOSFET's drain; a fourth p-channel MOSFET in trans-diode setup, its gate to the third p-channel MOSFET's gate and source to the supply rail; plus a current source placed between the fourth p-channel MOSFET's drain and ground.

Abstract: An electronic system is disclosed. The system includes a Gallium Nitride (GaN) semiconductor die and further including, entirely disposed on the GaN semiconductor die i) a voltage reference circuit including GaN semiconductor transistors, the voltage reference circuit configured to generate a reference voltage, and ii) an electronic component including GaN semiconductor transistors and configured to generate a power output based on the reference voltage.

Abstract: An electronic system is disclosed. The system includes a Gallium Nitride (GaN) semiconductor die and further including, entirely disposed on the GaN semiconductor die i) a voltage reference circuit including GaN semiconductor transistors, the voltage reference circuit configured to generate a reference voltage, and ii) an electronic component including GaN semiconductor transistors and configured to generate a power output based on the reference voltage.

Abstract: Disclosed herein is a startup current circuit, including a diode coupled transistor connected between an input node and a third node, and a feedback transistor connected between the input node and a first node, the feedback transistor having a control terminal coupled to receive a feedback voltage at a second node. A first current mirror has an input connected to the third node and an output connected to the second node. A second current mirror has an input connected to the first node and an output connected to the second node. A first sink transistor is connected between the first node and an output node through a resistor, and has a control terminal connected to a control node of the first current mirror. A second sink transistor is connected between the first node and the output node, and has a control terminal connected to the first node.

Abstract: A One Time Programmable (OTP) memory device includes a semiconductor die and an OTP memory cell integrated into the die. The die includes a channel layer and a barrier layer forming a heterostructure and a plurality of metallization levels over the heterostructure. The OTP memory cell includes a fuse element, having a low impedance value in a native unprogrammed state and a second impedance value in a programmed state, where the first impedance value is lower than the second impedance value; and a selector coupled in series to the fuse element and operable to cause the flow of a write current which brings the fuse element from the unprogrammed state to the programmed state in an irreversible manner. The fuse element is formed in one of the metallization levels of the die. The selector includes a High Electron Mobility Transistor (HEMT) at least partly formed in the heterostructure.

Abstract: According to an embodiment, a circuit for transistor gate stress testing is proposed. The circuit includes a first p-channel MOSFET with its drain linked to the transistor's gate; a second p-channel MOSFET coupling its source to the first p-channel MOSFET's source at a node and its drain to a supply voltage; a first n-channel MOSFET with its source to ground and drain to the transistor's gate; a second n-channel MOSFET with its source to ground and drain to the second p-channel MOSFET's gate; a third p-channel MOSFET with its source and drain bridging the node to the second n-channel MOSFET's drain; a fourth p-channel MOSFET in trans-diode setup, its gate to the third p-channel MOSFET's gate and source to the supply rail; plus a current source placed between the fourth p-channel MOSFET's drain and ground.

Abstract: A startup circuit includes a first circuit leg coupled between an input node and an output node and a second circuit leg coupled between the input node and the output node. The first circuit generates a first current and the second circuit leg sinks current from a first node based upon the first current. A third circuit leg is coupled between the input node and the output node and sources current to a second node based upon a voltage at the first node to thereby generate a feedback voltage at the second node. The first circuit leg increases the first current based upon the feedback voltage, in turn increasing the current sunk from the first node by the second circuit leg and increasing the current sourced to the second node by the third circuit leg to thereby generate a startup current at the output node.

Abstract: An integrated circuit device includes: one or more switches of a Buck converter; and a control circuit for the Buck converter, including: a comparator configured to compare a feedback voltage of the Buck converter with a compensation ramp voltage; a pulse generator configured to generate, in response to a rising edge in a comparator output signal, a pulse signal for controlling the Buck converter; a transconductance amplifier (TA) configured to generate, at an output terminal of the TA, a current proportional to a difference between a reference voltage and the feedback voltage; a capacitor coupled between an output terminal of the TA and a reference voltage node; and a ramp signal generator configured to generate the compensation ramp voltage by adding a voltage at the output terminal of the TA and a ramp voltage having a gradient proportional to a switching frequency of the Buck converter.

Abstract: A DC/DC converter including a low side and a high side is disclosed. The converter includes a first switching device being part of the low side, a low side current generator configured to generate a low side current flowing in the first switching device, a second switching device, a compensation resistor coupled in series to the second switching device, a valley current reference current generator configured to generate a valley current threshold current (Ivalclth) flowing in the second switching device and in the compensation resistor for obtaining a first voltage value, and a comparator configured to compare the first voltage value and a reference voltage for generating an error signal as a function of the comparison, the error signal controlling a conductivity of the first switching device of the low side.

Abstract: According to an embodiment, a bootstrap drive circuit for driving a bootstrap switch in a DC-DC converter is proposed. The bootstrap drive circuit includes a non-overlapping circuit, a first and a second capacitor, and a first and a second n-channel transistor. The non-overlapping circuit is configured to receive an input signal, the input signal being a function of a pulse width modulated (PWM) signal, wherein the input signal and the PWM signal are characterized by a first logic level, generate a first control signal from the input signal at a first output terminal of the non-overlapping circuit, the first control signal having the first logic level, and generate a second control signal from the input signal at a second output terminal of the non-overlapping circuit, the second control signal being characterized by a second logic level different from the first logic level.

Abstract: A Buck converter includes: a first power switch coupled between a supply voltage node and a switching node, where the first power switch is configure to be controlled by a first control signal; a boot-strap capacitor, where a first terminal of the boot-strap capacitor is coupled to the switching node; a first buffer coupled between a first node and a control terminal of the first power switch; a first switch circuit coupled between the first node and a second terminal of the boot-strap capacitor, where the first switch circuit is controlled by the first control signal, and is configured to pass through a first charging current provided by the boot-strap capacitor when the first control signal is asserted; and a slew-rate control capacitor, where a first terminal of the slew-rate control capacitor is coupled to the first node.

Abstract: A startup circuit includes a first circuit leg coupled between an input node and an output node and a second circuit leg coupled between the input node and the output node. The first circuit generates a first current and the second circuit leg sinks current from a first node based upon the first current. A third circuit leg is coupled between the input node and the output node and sources current to a second node based upon a voltage at the first node to thereby generate a feedback voltage at the second node. The first circuit leg increases the first current based upon the feedback voltage, in turn increasing the current sunk from the first node by the second circuit leg and increasing the current sourced to the second node by the third circuit leg to thereby generate a startup current at the output node.

Abstract: An integrated circuit device includes: one or more switches of a Buck converter; and a control circuit for the Buck converter including: a comparator configured to generate a comparator output signal by comparing a feedback voltage of the Buck converter with a compensation ramp voltage; a pulse generator configured to generate, in response to a rising edge in the comparator output signal, a pulse signal for controlling the Buck converter; a transconductance amplifier configured to generate, at an output terminal of the transconductance amplifier, a current proportional to a difference between a reference voltage and the feedback voltage; a capacitor coupled between the output terminal of the transconductance amplifier and a reference voltage node; and a ramp signal generator configured to generate the compensation ramp voltage by adding a voltage at the output terminal of the transconductance amplifier and a ramp voltage generated by the ramp signal generator.

Abstract: An integrated circuit device includes: one or more switches of a Buck converter; and a control circuit for the Buck converter, including: a comparator configured to compare a feedback voltage of the Buck converter with a compensation ramp voltage; a pulse generator configured to generate, in response to a rising edge in a comparator output signal, a pulse signal for controlling the Buck converter; a transconductance amplifier (TA) configured to generate, at an output terminal of the TA, a current proportional to a difference between a reference voltage and the feedback voltage; a capacitor coupled between an output terminal of the TA and a reference voltage node; and a ramp signal generator configured to generate the compensation ramp voltage by adding a voltage at the output terminal of the TA and a ramp voltage having a gradient proportional to a switching frequency of the Buck converter.