Abstract: A data regenerator for regenerating a data signal, including a convertor for converting a received data signal into a binary data signal in dependence on conversion parameters, an error corrector for correcting errors in the binary data signal based on error correction code contained in the binary data signal to produce a corrected binary data signal, and a performance monitor for comparing the corrected binary data signal with an uncorrected representation of the binary data signal to determine information about the relative number of logic“1”s and logic “0”s that have been corrected by the error corrector and output a feedback signal representative of the relative number, wherein the convertor adjusts at least some of the conversion parameters in dependance on the feedback signal.

Abstract: A data regenerator for regenerating a data signal, including a convertor for converting a received data signal into a binary data signal in dependence on conversion parameters, an error corrector for correcting errors in the binary data signal based on error correction code contained in the binary data signal to produce a corrected binary data signal, and a performance monitor for comparing the corrected binary data signal with an uncorrected representation of the binary data signal to determine information about the relative number of logic“1”s and logic “0”s that have been corrected by the error corrector and output a feedback signal representative of the relative number, wherein the convertor adjusts at least some of the conversion parameters in dependance on the feedback signal.

Abstract: A clock divider circuit for generating an output clock signal derived from an input clock signal with the output clock signal having a selected frequency and duty cycle. The clock divider circuit comprises a linear shift register with a feedback loop. Data is shifted through the stages of the linear shift register in response to the input clock signal being applied at a clock input port. The output clock signal is derived from the data outputs on selected stages in the linear shift register. In one aspect, the clock divider circuit divides a 667 MHz input clock signal to generate a 44 MHz output clock signal having a 50% duty cycle. In another aspect, the clock divider circuit divides a 669 MHz input clock signal to generate a 45 MHz output clock signal.