Abstract: Consistent with the present disclosure, an encoder circuit is provided at a transmit side of an optical fiber link that maps an input sequence of bits of fixed length k a sequence of symbols of a codeword of length n, such that the symbols of the codeword define a predetermined transmission probability distribution. Preferably, each symbol of the codeword is generated during a corresponding clock cycle, such that after n clock cycles, a complete codeword corresponding to the input bit sequence is output. On a receive end of the link, a decoder is provided that outputs the k-bit sequence every n clock cycles. Accordingly, buffers need not be provided at the output of the encoder and the input of the decoder, such that processing of the input sequence, codewords, and output sequence may be achieved efficiently without large buffers and complicated circuitry. Moreover, the input sequence, with any binary alphabet may be matched to a desired output distribution with any arbitrary alphabet.

Abstract: Consistent with the present disclosure, an encoder circuit is provided at a transmit side of an optical fiber link that maps an input sequence of bits of fixed length k a sequence of symbols of a codeword of length n, such that the symbols of the codeword define a predetermined transmission probability distribution. Preferably, each symbol of the codeword is generated during a corresponding clock cycle, such that after n clock cycles, a complete codeword corresponding to the input bit sequence is output. On a receive end of the link, a decoder is provided that outputs the k-bit sequence every n clock cycles. Accordingly, buffers need not be provided at the output of the encoder and the input of the decoder, such that processing of the input sequence, codewords, and output sequence may be achieved efficiently without large buffers and complicated circuitry. Moreover, the input sequence, with any binary alphabet may be matched to a desired output distribution with any arbitrary alphabet.

Abstract: Consistent with the present disclosure, multiple forward error correction (FEC) encoders are provided for encoding a respective one of a plurality of data streams. A mechanism is provided to mix or interleave portions of the encoded data such that each subcarrier carries information associated with each data stream, as opposed to each subcarrier carrying information associated with only a corresponding one of the data streams. As a result, both higher SNR and low SNR optical subcarriers carry such information, such that errors occurring during transmission are distributed and not concentrated or limited to information associated with a single data stream. Accordingly, at the receive end, each FEC decoder decodes information having a similar overall error rate. By balancing the error rates across each FEC encoder/decoder pair, the overall ability to correct errors improves compared to a system in which mixing or interleaving is not carried out.

Abstract: Consistent with the present disclosure independent phase and frequency clock recovery on each SC. Both leaf and hub perform digital clock recovery on each SC by increasing the Rx-ADC sampling rate by a few ppm (˜16 ppm), and using a delay compensating element, together with gapped clocks. The gaps and delay compensating elements are independent on each SC. The delay element is performed using the frequency domain DSP engine, where the frequency domain equalizer coefficients are modified with a delay compensating element Thus, each SC can have its own fine timing frequency and timing phase tuning, and fine tracking of its own jitter. When the delay compensating element, which, for example, may include a finite impulse response (FIR) filter, reaches the end of its range, a clock gap equal to an integer number of symbols is performed. The delay element can be reset by the same number of symbols providing continuous phase interpolation.

Abstract: Consistent with the present disclosure, an encoder circuit is provided at a transmit side of an optical fiber link that maps an input sequence of bits of fixed length k a sequence of symbols of a codeword of length n, such that the symbols of the codeword define a predetermined transmission probability distribution. Preferably, each symbol of the codeword is generated during a corresponding clock cycle, such that after n clock cycles, a complete codeword corresponding to the input bit sequence is output. On a receive end of the link, a decoder is provided that outputs the k-bit sequence every n clock cycles. Accordingly, buffers need not be provided at the output of the encoder and the input of the decoder, such that processing of the input sequence, codewords, and output sequence may be achieved efficiently without large buffers and complicated circuitry. Moreover, the input sequence, with any binary alphabet may be matched to a desired output distribution with any arbitrary alphabet.

Abstract: Consistent with the present disclosure, an encoder circuit is provided at a transmit side of an optical fiber link that maps an input sequence of bits of fixed length k a sequence of symbols of a codeword of length n, such that the symbols of the codeword define a predetermined transmission probability distribution. Preferably, each symbol of the codeword is generated during a corresponding clock cycle, such that after n clock cycles, a complete codeword corresponding to the input bit sequence is output. On a receive end of the link, a decoder is provided that outputs the k-bit sequence every n clock cycles. Accordingly, buffers need not be provided at the output of the encoder and the input of the decoder, such that processing of the input sequence, codewords, and output sequence may be achieved efficiently without large buffers and complicated circuitry. Moreover, the input sequence, with any binary alphabet may be matched to a desired output distribution with any arbitrary alphabet.

Abstract: Consistent with the present disclosure, an encoder circuit is provided at a transmit side of an optical fiber link that maps an input sequence of bits of fixed length k a sequence of symbols of a codeword of length n, such that the symbols of the codeword define a predetermined transmission probability distribution. Preferably, each symbol of the codeword is generated during a corresponding clock cycle, such that after n clock cycles, a complete codeword corresponding to the input bit sequence is output. On a receive end of the link, a decoder is provided that outputs the k-bit sequence every n clock cycles. Accordingly, buffers need not be provided at the output of the encoder and the input of the decoder, such that processing of the input sequence, codewords, and output sequence may be achieved efficiently without large buffers and complicated circuitry. Moreover, the input sequence, with any binary alphabet may be matched to a desired output distribution with any arbitrary alphabet.

Abstract: Consistent with the present disclosure, an encoder circuit is provided at a transmit side of an optical fiber link that maps an input sequence of bits of fixed length k a sequence of symbols of a codeword of length n, such that the symbols of the codeword define a predetermined transmission probability distribution. Preferably, each symbol of the codeword is generated during a corresponding clock cycle, such that after n clock cycles, a complete codeword corresponding to the input bit sequence is output. On a receive end of the link, a decoder is provided that outputs the k-bit sequence every n clock cycles. Accordingly, buffers need not be provided at the output of the encoder and the input of the decoder, such that processing of the input sequence, codewords, and output sequence may be achieved efficiently without large buffers and complicated circuitry. Moreover, the input sequence, with any binary alphabet may be matched to a desired output distribution with any arbitrary alphabet.

Abstract: Consistent with the present disclosure, an encoder circuit is provided at a transmit side of an optical fiber link that maps an input sequence of bits of fixed length k a sequence of symbols of a codeword of length n, such that the symbols of the codeword define a predetermined transmission probability distribution. Preferably, each symbol of the codeword is generated during a corresponding clock cycle, such that after n clock cycles, a complete codeword corresponding to the input bit sequence is output. On a receive end of the link, a decoder is provided that outputs the k-bit sequence every n clock cycles. Accordingly, buffers need not be provided at the output of the encoder and the input of the decoder, such that processing of the input sequence, codewords, and output sequence may be achieved efficiently without large buffers and complicated circuitry. Moreover, the input sequence, with any binary alphabet may be matched to a desired output distribution with any arbitrary alphabet.

Abstract: A low-density parity-check (LDPC) decoder may comprise a shift register configured to receive LDPC coded data, perform an iteration associated with decoding the LDPC coded data, and provide a result of performing the iteration. The shift register may include a quantity of lanes corresponding to a quantity of data words received by the shift register at a particular clock cycle, a quantity of stages corresponding to a quantity of clock cycles needed to perform the iteration, a quantity of storage elements, associated with storing the data words during the iteration, and a set of check node elements associated with updating the data words during the iteration. The quantity of stages times the quantity of lanes may be greater than the quantity of storage elements by a particular number of storage elements. The particular number of storage elements may be displaced by the set of check node elements.

Abstract: A low-density parity-check (LDPC) decoder may receive LDPC coded data. The LDPC decoder may perform a decoding iteration associated with decoding the LDPC coded data. The decoding iteration may be performed by processing a group of layers. Each layer may include a corresponding set of check node elements, and may be processed by causing each check node element, of the set of check node elements corresponding to the layer, to update a set of variable node elements, connected to the check node element and associated with the LDPC coded data, based on a check node function associated with the check node element. The decoding iteration may be performed such that each layer is processed in parallel, and such that each check node element updates the corresponding set of variable node elements in parallel. The LDPC decoder may provide a result of performing the decoding iteration.

Abstract: An optical receiver may receive a data stream, and may decode the data stream using a first iterative forward error correction (FEC) decoder. The optical receiver may determine whether to further decode the data stream using the first iterative FEC decoder or a second iterative FEC decoder that is different from the first iterative FEC decoder. The optical receiver may selectively perform a first action or a section action based on determining whether to further decode the data stream. The first action may include providing the data stream to the first iterative FEC decoder or the second iterative FEC decoder for further decoding when the data stream is to be further decoded. The second action may include preventing the data stream from being provided to the first iterative FEC decoder or the second iterative FEC decoder when the data stream is not to be further decoded.

Abstract: An optical receiver may receive input signals carried by sub-carriers, and may apply test phases to each input signal. The optical receiver may determine error values, associated with test phases, for each input signal. The optical receiver may calculate updated metric values, associated with the test phases, for a particular input signal, based on a first error value and a second error value. The first error value may be associated with a first sub-carrier, and the second error value may be associated with a second sub-carrier. The optical receiver may compare the updated metric values associated with the particular input signal, and may determine a test phase that represents an estimated phase, associated with the particular input signal, based on the comparison. The optical receiver may determine a phase estimate value based on the test phase, and may provide the phase estimate value to modify the particular input signal.

Abstract: An optical receiver may receive input signals carried by respective sub-carriers. The optical receiver may determine, based on the input signals, a compensation value to be used to modify an input signal. The optical receiver may use the compensation value to adjust the input signal to form a modified input signal. The compensation value may be used to modify a frequency or a phase of the input signal. The optical receiver may determine, based on the modified input signal, a phase estimate value that represents an estimated phase associated with the input signal. The optical receiver may combine the compensation value and the phase estimate value to form a phase adjustment signal, may combine the input signal and the phase adjustment signal to form an output signal, and may output the output signal.

Abstract: An optical receiver may receive a data stream, and may decode the data stream using a first iterative forward error correction (FEC) decoder. The optical receiver may determine whether to further decode the data stream using the first iterative FEC decoder or a second iterative FEC decoder that is different from the first iterative FEC decoder. The optical receiver may selectively perform a first action or a section action based on determining whether to further decode the data stream. The first action may include providing the data stream to the first iterative FEC decoder or the second iterative FEC decoder for further decoding when the data stream is to be further decoded. The second action may include preventing the data stream from being provided to the first iterative FEC decoder or the second iterative FEC decoder when the data stream is not to be further decoded.

Abstract: A low-density parity-check (LDPC) decoder may receive LDPC coded data. The LDPC decoder may perform a decoding iteration associated with decoding the LDPC coded data. The decoding iteration may be performed by processing a group of layers. Each layer may include a corresponding set of check node elements, and may be processed by causing each check node element, of the set of check node elements corresponding to the layer, to update a set of variable node elements, connected to the check node element and associated with the LDPC coded data, based on a check node function associated with the check node element. The decoding iteration may be performed such that each layer is processed in parallel, and such that each check node element updates the corresponding set of variable node elements in parallel. The LDPC decoder may provide a result of performing the decoding iteration.

Abstract: A low-density parity-check (LDPC) decoder may comprise a shift register configured to receive LDPC coded data, perform an iteration associated with decoding the LDPC coded data, and provide a result of performing the iteration. The shift register may include a quantity of lanes corresponding to a quantity of data words received by the shift register at a particular clock cycle, a quantity of stages corresponding to a quantity of clock cycles needed to perform the iteration, a quantity of storage elements, associated with storing the data words during the iteration, and a set of check node elements associated with updating the data words during the iteration. The quantity of stages times the quantity of lanes may be greater than the quantity of storage elements by a particular number of storage elements. The particular number of storage elements may be displaced by the set of check node elements.

Abstract: In one implementation, a device may include a voltage regulator circuit, a data processing circuit, and an error correction circuit, where the error correction circuit may correct errors in data processed by the data processing circuit to obtain error-corrected data and output an error-corrected version of the processed data. Additionally, an error monitor circuit may output an error signal indicative of a level of the errors in the processed data. A control circuit may receive the error signal and control the voltage regulator circuit to adjust, based on the error signal, the supply voltage to the data processing circuit. In some implementations, the control circuit may also base its decision to control the voltage regulator circuit based on available timing margins in the data processing circuit.

Abstract: An optical receiver may receive input signals carried by sub-carriers, and may apply test phases to each input signal. The optical receiver may determine error values, associated with test phases, for each input signal. The optical receiver may calculate updated metric values, associated with the test phases, for a particular input signal, based on a first error value and a second error value. The first error value may be associated with a first sub-carrier, and the second error value may be associated with a second sub-carrier. The optical receiver may compare the updated metric values associated with the particular input signal, and may determine a test phase that represents an estimated phase, associated with the particular input signal, based on the comparison. The optical receiver may determine a phase estimate value based on the test phase, and may provide the phase estimate value to modify the particular input signal.

Abstract: An optical receiver may receive input signals carried by respective sub-carriers. The optical receiver may determine, based on the input signals, a compensation value to be used to modify an input signal. The optical receiver may use the compensation value to adjust the input signal to form a modified input signal. The compensation value may be used to modify a frequency or a phase of the input signal. The optical receiver may determine, based on the modified input signal, a phase estimate value that represents an estimated phase associated with the input signal. The optical receiver may combine the compensation value and the phase estimate value to form a phase adjustment signal, may combine the input signal and the phase adjustment signal to form an output signal, and may output the output signal.