Patents by Inventor Sanford Shao Fu Chu

Sanford Shao Fu Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabrication an integrated circuit
    Patent number: 8003529
    Abstract: A method of forming an integrated circuit is disclosed. The method includes providing a substrate and forming on the substrate a shield structure comprising a shield member and a ground strap. The shield member comprises a non-metallic portion, and the ground strap comprises a metallic portion.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: August 23, 2011
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Suh Fei Lim, Kok Wai Chew, Sanford Shao-Fu Chu, Michael Chye Huat Cheng
  • INTEGRATED CIRCUIT SHIELD STRUCTURE AND METHOD OF FABRICATION THEREOF
    Publication number: 20100120244
    Abstract: A method of forming an integrated circuit is disclosed. The method includes providing a substrate and forming on the substrate a shield structure comprising a shield member and a ground strap. The shield member comprises a non-metallic portion, and the ground strap comprises a metallic portion.
    Type: Application
    Filed: January 25, 2010
    Publication date: May 13, 2010
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Suh Fei LIM, Kok Wai CHEW, Sanford Shao-Fu CHU, Michael Chye Huat CHENG
  • Integrated circuit shield structure
    Patent number: 7652355
    Abstract: Embodiments of the invention provide an integrated circuit structure comprising: a substrate; a shield structure comprising a shield member and a ground strap formed on the substrate, wherein the shield member comprises a non-metallic portion, and the ground strap comprises a metallic portion.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: January 26, 2010
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Suh Fei Lim, Kok Wai Chew, Sanford Shao-Fu Chu, Michael Chye Huat Cheng
  • Method to form a high K dielectric gate insulator layer, a metal gate structure, and self-aligned channel regions, post source/drain formation
    Patent number: 6300201
    Abstract: A process of fabricating a sub-micron MOSFET device, featuring a high dielectric constant gate insulator layer, and a metal gate structure, has been developed. Processes performed at temperatures detrimental to the high dielectric, gate insulator layer, such as formation of spacers on the sides of subsequent gate structures, as well as formation of source/drain regions, are introduced prior to the formation of the high dielectric, gate insulator layer. This is accomplished via use of a dummy gate structure, comprised of silicon nitride, used as a mask to define the source/drain regions, and used as the structure in which sidewall spacers are formed on. After selective removal of the dummy gate structure, creating an opening in an interlevel dielectric layer exposing the MOSFET channel region, deposition of the high dielectric, gate insulator layer, on the surface of the MOSFET channel region, is performed.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: October 9, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kai Shao, Jiong Zhang, Qing Hua Zhang, Yi Min Wang, Sanford Shao Fu Chu