Abstract: A lower cross member for a vehicle is disposed on a floor of a vehicle. The lower cross member includes a core member and a reinforcing layer. The core member is made of a composite material containing 70 wt. % or more of unidirectional carbon fibers, and the reinforcing layer is made of a composite material containing 70 wt. % or more of fiberglass.

Abstract: A deep trench layout implementation for a semiconductor device is provided. The semiconductor device includes an isolation film with a shallow depth, an active area, and a gate electrode formed in a substrate; a deep trench isolation surrounding the gate electrode and having one or more trench corners; and a gap-fill insulating film formed inside the deep trench isolation. The one or more trench corners is formed in a slanted shape from a top view.

Abstract: A deep trench layout implementation for a semiconductor device is provided. The semiconductor device includes an isolation film with a shallow depth, an active area, and a gate electrode formed in a substrate; a deep trench isolation surrounding the gate electrode and having one or more trench corners; and a gap-fill insulating film formed inside the deep trench isolation. The one or more trench corners is formed in a slanted shape from a top view.

Abstract: A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.

Abstract: A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.

Abstract: A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).

Abstract: A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set.

Abstract: A non-volatile memory device including a cell array, which includes a plurality of memory cells, and a sense amplification circuit. The sense amplification circuit is configured to receive a data voltage of a memory cell, a first reference voltage and a second reference voltage during a data read operation of the memory cell, generate differential output signals based on a voltage level difference between the data voltage and the first and second reference voltages, and output the differential output signals as data read from the memory cell.

Abstract: A stacked semiconductor memory device comprises memory cell array layers that are stacked in an inverted wedge shape and have different redundancy sizes from each other. The stacked semiconductor memory device has space for vertical connection between layers, a relatively small size, and a relatively high yield.

Abstract: A semiconductor memory device includes a cell array having a plurality of memory cells, each memory cell including a resistive element and a cell transistor between a bit line and a source line, and a source line voltage supply unit configured to supply, in a normal mode, a reference source line voltage to the source line, and in a test mode, a first source line voltage to the source line when data in a first state is recorded and a second source line voltage to the source line when data in a second state is recorded, the first source line voltage being lower than the reference source line voltage, and the second source line voltage being higher than the reference source line voltage.

Abstract: A method of changing a parameter in a semiconductor device is provided. The method includes receiving and storing data in a storage region; and changing at least one between a DC characteristic and an AC timing characteristic of a parameter, used to access a non-volatile memory cell included in a memory core of the semiconductor device, according to the data stored in the storage.

Abstract: A stacked semiconductor memory device includes an error correction code (ECC) controller that controls the number of bits in an ECC word and corrects errors in memory cell array layers using the ECC word.

Abstract: A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit.

Abstract: A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. The MTJ element includes a free layer, a barrier layer and a pinned layer. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set.

Abstract: A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups.

Abstract: A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells.

Abstract: A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.

Abstract: A device, e.g., a semiconductor memory device, includes a plurality of memory cells, each configured to store at least one data bit and a plurality of error correction code (ECC) cells configured to redundantly store ECC bits for the memory cells. According to some embodiments, the plurality of ECC cells includes a plurality of pairs of ECC cells configured to store an ECC bit and a complement thereof. According to further embodiments, the plurality of ECC cells includes a plurality of groups of at least three ECC cells configured to store identical copies of an ECC bit.

Abstract: A semiconductor memory device includes a cell array having a plurality of memory cells, each memory cell including a resistive element and a cell transistor between a bit line and a source line, and a source line voltage supply unit configured to supply, in a normal mode, a reference source line voltage to the source line, and in a test mode, a first source line voltage to the source line when data in a first state is recorded and a second source line voltage to the source line when data in a second state is recorded, the first source line voltage being lower than the reference source line voltage, and the second source line voltage being higher than the reference source line voltage.

Abstract: A semiconductor device, a semiconductor system including the same, and a voltage supply method of the semiconductor device are provided. The semiconductor device includes at least two semiconductor memory devices and a voltage supply controller configured to selectively supply a voltage to each of the at least two semiconductor memory devices.