Patents by Inventor Sang-Bin Ahn

Sang-Bin Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240237334
    Abstract: A semiconductor memory device with improved performance and reliability is provided. The semiconductor memory device includes a substrate having a cell region and a peripheral region, a cell region isolation layer that separates the cell region from the peripheral region, and a plurality of cell gate structures, each including a cell gate electrode that extends in a first direction. The cell region includes a plurality of active areas that extend in a second direction different from the first direction, and are between a respective cell element isolation layer and the cell region isolation layer. Each of the active areas includes a first portion and a second portion separated by the cell gate structure, the second portion of the active area is on both sides of a respective one of the first portion of the active area. The active areas includes a normal active area and a dummy active area.
    Type: Application
    Filed: July 11, 2023
    Publication date: July 11, 2024
    Inventors: Kang In Kim, Kyoung Hwan Kim, Young Woo Son, Sang-Bin Ahn, Sang Min Lee, Young-Seung Cho
  • Patent number: 8729658
    Abstract: Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: May 20, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Soo Kim, Kwang-Youl Chun, Sang-Bin Ahn
  • Publication number: 20130187291
    Abstract: Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer.
    Type: Application
    Filed: March 7, 2013
    Publication date: July 25, 2013
    Inventors: Bong-Soo Kim, Kwang-Youl Chun, Sang-Bin Ahn
  • Patent number: 8405185
    Abstract: Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: March 26, 2013
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Bong-Soo Kim, Kwang-Youl Chun, Sang-Bin Ahn
  • Publication number: 20120273791
    Abstract: A polycrystalline semiconductor layer is formed on a cell active region and a peripheral active region of a substrate. A buried gate electrode is formed in the substrate in the cell active region at a level below the polycrystalline semiconductor layer after forming the polycrystalline semiconductor layer. A gate electrode is formed on the substrate in the peripheral active region from the polysilicon semiconductor layer after forming the buried gate electrode.
    Type: Application
    Filed: July 11, 2012
    Publication date: November 1, 2012
    Inventors: Bongsoo Kim, Chul Lee, Deoksung Hwang, Sang-Bin Ahn
  • Publication number: 20120139021
    Abstract: A semiconductor memory device includes a transistor having a channel region buried in a substrate and source/drain regions formed to provide low contact resistance. A field isolation structure is formed in the substrate to define active structures. The field isolation structure includes a gap-fill pattern, a first material layer surrounding the gap-fill pattern, and a second material layer surrounding at least a portion of the first material layer. Each active structure includes a first active pattern having a top surface located beneath the level of the top surface of the field isolation structure, and a second active pattern disposed on the first active pattern and whose top is located above the level of the top surface of the field isolation structure.
    Type: Application
    Filed: September 23, 2011
    Publication date: June 7, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Hyun Kim, Deok-Sung Hwang, Yun-Jae Lee, Chul Lee, Yoon-Taek Jang, Chang-Hoon Jeon, Sang-Bin Ahn, Jun-Hyeok Ahn
  • Publication number: 20110175229
    Abstract: Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer.
    Type: Application
    Filed: November 12, 2010
    Publication date: July 21, 2011
    Inventors: Bong-Soo Kim, Kwang-Youl Chun, Sang-Bin Ahn
  • Publication number: 20110171800
    Abstract: A polycrystalline semiconductor layer is formed on a cell active region and a peripheral active region of a substrate. A buried gate electrode is formed in the substrate in the cell active region at a level below the polycrystalline semiconductor layer after forming the polycrystalline semiconductor layer. A gate electrode is formed on the substrate in the peripheral active region from the polysilicon semiconductor layer after forming the buried gate electrode.
    Type: Application
    Filed: November 12, 2010
    Publication date: July 14, 2011
    Inventors: Bongsoo Kim, Chul Lee, Deoksung Hwang, Sang-Bin Ahn