Abstract: A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed.

Abstract: Disclosed herein is an anaerobic digester.

Abstract: The present invention can provide frying oil with the enzymatic interesterification reaction, in which trans fatty acid is not formed in the process different from the existing partially hydrogenerated oil and the frying oil contains less than 1% of trans fatty acid content and less than 27% of palmitic acid based on total fatty acid content and has solid fat content at temperature of 37.8° C. and melting point corresponding to that of partially hydrogenerated oil. Accordingly, the frying oil of the present invention is eco-friend and has lower trans fatty acid compared to the existing partially hydrogenerated oil and has higher triglyceride content without side reaction, and is also nutritionally excellent since it has lower palmitic acid content than natural palm oil which is usually used as a substitute for the existing frying oil such as partially hydrogenerated oil, and has taste corresponding to partially hydrogenerated oil.

Abstract: There is provided a semiconductor light emitting device that minimizes reflection or absorption of emitted light, maximizes luminous efficiency with the maximum light emitting area, enables uniform current spreading with a small area electrode, and enables mass production with high reliability and high quality. A semiconductor light emitting device according to an aspect of the invention includes first and second conductivity type semiconductor layers, an active layer formed therebetween, first electrode layer, and a second electrode part electrically connecting the semiconductor layers. The second electrode part includes an electrode pad unit, an electrode extending unit, and an electrode connecting unit connecting the electrode pad unit and electrode extending unit.

Abstract: The present invention can provide margarine oil with the enzymatic interesterification reaction, in which trans fatty acid, different from the existing partially hydrogenerated oil, is not formed in the process, and it has solid fat value profile and melting point corresponding to that of partially hydrogenerated oil and contains less than 1% of trans fatty acid, less than 27% of palmitic acid, more than 99% of triglyceride, less than 1% of diglyceride and monoglyceride, less than 1% of trans fatty acid and based on total fatty acid content.

Abstract: A semiconductor device is provided. The semiconductor device includes a first gate line, a second gate line, a first contact electrode, first dummy gates, a second gate pad, and a second contact electrode. The first gate line is formed on a semiconductor substrate and the second gate line of a spacer shape is formed on the sidewalls of the first gate line with a thin insulating layer interposed therebetween. The first contact electrode is vertically connected with the first gate line. The first dummy gates are formed in array spaced a predetermined interval from the first gate line on the semiconductor substrate. The second gate pad of a spacer shape is formed on the sidewalls of the first dummy gates with a thin insulating layer interposed therebetween. The second gate pad is connected to the second gate line and is also gap-filled between the first dummy gates. The second contact electrode is vertically connected with the second gate pad.

Abstract: A nonvolatile memory device and method for fabricating the same are provided. The nonvolatile memory device includes an active region; a source region formed in the active region; a source line formed on the source region and electrically connected with the source region, to cross over the active region; word lines aligned at each sidewall of the source line to cross over the active region in parallel with the source line; and a charge storage layer interposed between the word lines and the active region. Since the word lines are formed at both sides of the source line using an anisotropic etch-back process, without photolithography, the area of a unit cell can be reduced.

Abstract: There is provided a surface treatment method of a group III nitride semiconductor including: providing a group III nitride semiconductor including a first surface having a group III polarity and a second surface opposing the first surface and having a nitrogen polarity; and irradiating a laser beam onto the second surface to change the nitrogen polarity of the second surface to the group III polarity.

Abstract: Disclosed are a flash memory device having a silicon-oxide-nitride-oxide-silicon (SONOS) structure and a method of manufacturing the same. The flash memory device includes source and drain diffusion regions separated from each other on opposite sides of a trench in an active region of a semiconductor substrate, a control gate inside the trench and protruding upward from the substrate, a charge storage layer between the control gate and an inner wall of the trench, and a pair of insulating spacers formed on opposite sidewalls of the control gate with the charge storage layer therebetween. Here, the charge storage layer has an oxide-nitride-oxide (ONO) structure. Further, the depth of the trench from the surface of the substrate is greater than that of each of the source and drain diffusion regions.

Abstract: A flash memory device includes a source region formed in an active region of a semiconductor substrate; a recessed region formed in the active region on either side of the source region, the recessed region including a recess surface having sidewalls; floating gates formed at the sidewalls of the recess surface by interposing a tunnel insulating film; a source line formed on the source region across the active region; and control gate electrodes formed at sidewalls of the source line across a portion of the active region where the floating gates are formed. The floating gates and the control gate electrodes are formed by anisotropically etching a conformal conductive film to have a spacer structure. Cell transistor size can be reduced by forming a deposition gate structure at both sides of the source line, and short channel effects can be minimized by forming the channel between the sidewalls of a recess surface.

Abstract: A flash memory device includes a floating gate formed on a substrate, sidewall gates formed on sidewalls of the floating gate, an interlayer insulating layer formed the floating gate and the sidewall gates, and a control gate formed on the interlayer insulating layer. The fabricating method of a flash memory device includes forming a floating gate on a substrate, forming sidewall gates at sidewalls of the floating gate, forming an interlayer insulating layer on the floating gate and the sidewall gates, and forming a control gate on the interlayer insulating layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a first gate line, a second gate line, a first contact electrode, first dummy gates, a second gate pad, and a second contact electrode. The first gate line is formed on a semiconductor substrate and the second gate line of a spacer shape is formed on the sidewalls of the first gate line with a thin insulating layer interposed therebetween. The first contact electrode is vertically connected with the first gate line. The first dummy gates are formed in array spaced a predetermined interval from the first gate line on the semiconductor substrate. The second gate pad of a spacer shape is formed on the sidewalls of the first dummy gates with a thin insulating layer interposed therebetween. The second gate pad is connected to the second gate line and is also gap-filled between the first dummy gates. The second contact electrode is vertically connected with the second gate pad.

Abstract: Method for fabricating a semiconductor device, including the steps of providing a first conductive type semiconductor substrate having a cell region and a logic region defined thereon, forming a first insulating film, second conductive type polysilicon, and a second insulating film in succession on the semiconductor substrate, selectively removing the first insulating film, the polysilicon, and the second insulating film, to form a floating gate pattern at the cell region, elevating a temperature initially in a state O2 gas is injected, maintaining a fix temperature, and dropping the temperature in a state N2 gas is injected, to form a gate oxide film on a surface of the semiconductor substrate at the logic region, and forming a gate electrode pattern at each of the cell region and the logic region, whereby preventing a threshold voltage of a semiconductor device from dropping due to infiltration of impurities from doped polysilicon at the cell region to the active channel region.

Abstract: A semiconductor device is provided. The semiconductor device includes a first gate line, a second gate line, a first contact electrode, first dummy gates, a second gate pad, and a second contact electrode. The first gate line is formed on a semiconductor substrate and the second gate line of a spacer shape is formed on the sidewalls of the first gate line with a thin insulating layer interposed therebetween. The first contact electrode is vertically connected with the first gate line. The first dummy gates are formed in array spaced a predetermined interval from the first gate line on the semiconductor substrate. The second gate pad of a spacer shape is formed on the sidewalls of the first dummy gates with a thin insulating layer interposed therebetween. The second gate pad is connected to the second gate line and is also gap-filled between the first dummy gates. The second contact electrode is vertically connected with the second gate pad.

Abstract: A flash memory device includes a source region formed in an active region of a semiconductor substrate; a recessed region formed in the active region on either side of the source region, the recessed region including a recess surface having sidewalls; floating gates formed at the sidewalls of the recess surface by interposing a tunnel insulating film; a source line formed on the source region across the active region; and control gate electrodes formed at sidewalls of the source line across a portion of the active region where the floating gates are formed. The floating gates and the control gate electrodes are formed by anisotropically etching a conformal conductive film to have a spacer structure. Cell transistor size can be reduced by forming a deposition gate structure at both sides of the source line, and short channel effects can be minimized by forming the channel between the sidewalls of a recess surface.

Abstract: Provided is a method of manufacturing a vertical LED, the method including the steps of: preparing a sapphire substrate; forming a light emitting structure in which an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer are sequentially laminated on the sapphire substrate; forming a p-electrode on the p-type nitride semiconductor layer; forming a structure support layer on the p-electrode; removing the sapphire substrate through an LLO (laser lift-off) process; isolating the light emitting structure into unit LED elements through an ISO (isolation) process; and forming an n-electrode on each of the n-type nitride semiconductor layers of the isolated light emitting structures.

Abstract: A liquid crystal display module and an assembling method thereof are disclosed. The liquid crystal display module includes a panel guide for supporting a liquid crystal panel, the panel guide including a first fastening portion, support side members for holding opposite sides of a lamp irradiating light to the liquid crystal panel, respectively, each of the support side members including a second fastening portion having a foreign substance shield, and a bottom case including a third fastening portion having a case hole formed through a side surface of the bottom case, to receive the foreign substance shield.

Abstract: Disclosed are a semiconductor light emitting device, which can improve characteristics of the semiconductor light emitting device such as a forward voltage characteristic and a turn-on voltage characteristic, increase light emission efficiency by lowering an input voltage, and increase reliability of the semiconductor light emitting device by a low-voltage operation, and a method of manufacturing the same. The semiconductor light emitting device includes: an n-type GaN semiconductor layer; an active layer formed on a gallium face of the n-type GaN semiconductor layer; a p-type semiconductor layer formed on the active layer; and an n-type electrode formed on a nitrogen face of the n-type GaN semiconductor layer and including a lanthanum (La)-nickel (Ni) alloy.

Abstract: There is provided a semiconductor light emitting device that minimizes reflection or absorption of emitted light, maximizes luminous efficiency with the maximum light emitting area, enables uniform current spreading with a small area electrode, and enables mass production with high reliability and high quality. A semiconductor light emitting device according to an aspect of the invention includes first and second conductivity type semiconductor layers, an active layer formed therebetween, first electrode layer, and a second electrode part electrically connecting the semiconductor layers. The second electrode part includes an electrode pad unit, an electrode extending unit, and an electrode connecting unit connecting the electrode pad unit and electrode extending unit.

Abstract: A backlight unit for a display device includes a frame; a circuit board extending from an end of and on a first surface of the frame; lamps over the frame; an inverter on a second surface of the frame connected to an end of each of the lamps via a first hole through the frame; and balancing elements on the circuit board for balancing a current through each of the lamps.