Abstract: In some embodiments, a memory system includes a memory device and a host configured to transmit, to the memory device, a command and address (C/A) signal and a clock signal, and to transmit or receive data signals to or from the memory device. Each command that is configured to access the memory device is associated with an access timing parameter. The memory device includes an access parameter timer configured to measure an actual timing value of the access timing parameter, a spec register configured to provide a spec timing value defining an effective timing of the access timing parameter, a comparison circuit configured to compare the actual timing value and the spec timing value, and a mode register configured to store an access timing violation flag that is read by the host when the actual timing value deviates from the spec timing value by exceeding a predetermined range.

Abstract: A gate insulating layer in a semiconductor device and a method of forming the same. In one example embodiment, a gate insulating layer in a semiconductor device includes an oxide layer, a first oxynitride layer formed between a semiconductor substrate and the oxide layer, and a second oxynitride layer formed on the oxide layer.