Abstract: Provided is an integrated circuit device including a substrate, a plurality of semiconductor patterns on a first surface of the substrate, a gate electrode extending in a first direction and surrounding the semiconductor patterns, a source/drain region disposed on one side of the gate electrode, a vertical power wiring layer extending in a second direction, a liner structure including a first liner and a second liner, the first liner disposed on a lower portion of a sidewall of the vertical power wiring layer and including a first insulating material, and the second liner disposed on an upper portion of the sidewall of the vertical power wiring layer and including a second insulating material, a first contact disposed on the source/drain region and the vertical power wiring layer, and a back wiring structure disposed on a second surface of the substrate and electrically connected to the vertical power wiring layer.

Abstract: A precursor for preparing a chemical mechanical polishing pad includes a prepolymer, a disulfide-containing component, and a curative. The chemical mechanical polishing pad prepared from the precursor includes a disulfide bridge in a polymer matrix. The disulfide bridge may include a disulfide bond capable of undergoing a chain exchange reaction at temperatures experienced during chemical mechanical polishing processes, resulting in rearrangement of nearby disulfide bonds during the chemical mechanical polishing processes rather than breakage of these bonds.

Abstract: A semiconductor device includes a substrate having a first and second active patterns therein, first and second source/drain patterns extending on the first and second active patterns, respectively, and an active contact on the first and second source/drain patterns. An upper contact is provided, which extends from the active contact towards the substrate, and between the first and second active patterns. A lower power interconnection line is provided, which is buried in a lower portion of the substrate and includes: a buried interconnection portion having a line shape, and a lower contact portion extending vertically from the buried interconnection portion to a bottom surface of the upper contact. A barrier pattern is provided, which extends between the lower contact portion and the upper contact, but not between the buried interconnection portion and the lower contact portion.

Abstract: An example image forming apparatus includes a simplex path for conveying printing medium passing through a fixing unit provided in a main body to a discharge port of the main body, a duplex path for turning over printing medium and conveying the printing medium to the simplex path, and a discharge unit for selectively conveying a first printing medium and a second printing medium in different directions, wherein the first printing medium includes an image formed on one surface passing through the simplex path, and the second printing medium includes an image formed on two surfaces and passing through the simplex path after passing through the duplex path.

Abstract: A chemical mechanical polishing pad comprising a polishing portion, the polishing portion comprising: a polymeric body; a plurality of polymer particles embedded within the body of the polymeric body, wherein at least a portion of the plurality of polymer particles is at least partially exposed at a surface of the polymeric body; and a plurality of pores at the surface of the polymeric body.

Abstract: A sensor cleaning device to clean a sensor to detect a printable medium on a transferring path. The sensor cleaning device includes a cleaning lever, and a driver. The cleaning lever is coupled to a cleaner at an end of the cleaning lever. The driver is coupled to the cleaning lever and is to drive the cleaning lever to move the cleaner from a first position to a second position and back to the first position, the first position being away from the transferring path and the second position being in contact with the sensor.

Abstract: A method of stably and precisely attaching substrates and an apparatus for stably and precisely attaching substrates, the method including: placing a substrate, attached with a release film, on a shuttle stage; peeling the release film from the substrate; a transferring unit lifting the substrate from the shuttle stage; a gas supplier spraying gas toward the substrate so that the substrate is convexly curved in a direction away from the gas supplier; the substrate transferred into a chamber by the transferring unit; placing the substrate on a main stage in the chamber; and attaching the substrate to an adherend.

Abstract: A method of stably and precisely attaching substrates and an apparatus for stably and precisely attaching substrates, the method including: placing a substrate, attached with a release film, on a shuttle stage; peeling the release film from the substrate; a transferring unit lifting the substrate from the shuttle stage; a gas supplier spraying gas toward the substrate so that the substrate is convexly curved in a direction away from the gas supplier; the substrate transferred into a chamber by the transferring unit; placing the substrate on a main stage in the chamber; and attaching the substrate to an adherend.

Abstract: Disclosed herein is a task scheduling method for a priority-based real-time operating system in a multicore environment, which solves problems occurring in real-time multicore task scheduling which employs a conventional decentralized scheme. In the task scheduling method, one or more scheduling algorithm candidates for sequential tasks are combined with one or more scheduling algorithm candidates for parallel tasks. Respective task scheduling algorithm candidates generated at combining, are simulated and performances of the candidates are evaluated based on performance evaluation criteria. A task scheduling algorithm exhibiting best performance is selected from among results obtained at evaluating the performances.

Abstract: Disclosed herein is a task scheduling method for a priority-based real-time operating system in a multicore environment, which solves problems occurring in real-time multicore task scheduling which employs a conventional decentralized scheme. In the task scheduling method, one or more scheduling algorithm candidates for sequential tasks are combined with one or more scheduling algorithm candidates for parallel tasks. Respective task scheduling algorithm candidates generated at combining, are simulated and performances of the candidates are evaluated based on performance evaluation criteria. A task scheduling algorithm exhibiting best performance is selected from among results obtained at evaluating the performances.

Abstract: Provided is a method for statically allocating a stack based on multi thread. The method includes arbitrarily dividing a heap area and a stack area; allocating a stack space of each thread to the heap area at a predetermined size before executing the thread; swapping the stack of each thread in a stack area and measuring a stack size during executing the corresponding thread; and varying the heap area according to the measured stack size and reallocating the stack space of each thread allocated to the heap area. The provided executes programs without analyzing a complicated source code to expect the proper stack size of the thread while effectively using the stack memory during execution time as maximally as possible and statically allocates a stack memory based on the used amount of the measured stack to remove an overhead that moves the stack.

Abstract: A dynamic address allocation method includes allowing a new terminal that desires to participate in the ad hoc network to broadcast an address block request message to neighbor terminals in order to be allocated with an address; allowing the new terminal to receive a plurality of address block reply messages from the neighbor terminals; allowing the new terminal to transmit an address block confirmation message to a 1-hop neighbor terminal in a normal state that has a largest address block on the basis of the plurality of address block reply messages; allowing the new terminal to receive an address block completion message, which includes bitmap information for an available address block, from the 1-hop neighbor terminal; and allowing the new terminal to be allocated with the address and to change its terminal state from an alone state to a normal state.

Abstract: A footgear sole is formed of a material with resiliency and has a uniform thickness over the entire area thereof inclusive of a heel portion. An incision is formed in the ground plane of the sole along a straight line extending via one point present at a nearly central point of the ground plane, in a longitudinal direction of the footgear. Further, a plurality of incisions are formed in the ground plane along segments defining a plurality of similar quadrilaterals each having two corners thereof placed on the straight line, in a manner being opposed to each other across the one point, and another two corners thereof placed on a second straight line present in an assumed plane including the ground plane and orthogonal to the first straight line via the one point, in a manner being opposed to each other across the one point. At walking, the sole can be easily deformed along the incisions, depending on force received from a foot of the wearer or the ground.