Abstract: A memory device includes one or more layers of parallel strings of ferroelectric gate transistors on a substrate, each layer of parallel strings including a plurality of parallel line-shaped active regions and a plurality of word lines extending in parallel transversely across the active regions and disposed on ferroelectric patterns on the active regions. A string select gate line may extend transversely across the active regions in parallel with the word lines. A ground select gate line may extend transversely across the active regions in parallel with the word lines.

Abstract: A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of rows and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes.

Abstract: In fabricating a phase changeable memory device, an insulating layer with an opening extending therethrough is formed on a substrate. A conductive structure is formed in the opening. The conductive structure includes a first conductive plug on opposing sidewalls of the opening and a surface therebetween and a second plug on the first conductive plug. The first conductive plug is between the second plug and the sidewalls of the opening and between the second plug and the surface therebetween. A lower electrode is formed on the first conductive plug, on the second plug, and on the insulating layer. The lower electrode extends outside the opening in the insulating layer. A phase changeable material layer is formed on the lower electrode, and an upper electrode is formed on the phase changeable material layer opposite the lower electrode.

Abstract: A ferroelectric memory device and a method of forming the same are provided. At least two lower electrode patterns are formed on an interlayer insulating layer covering a semiconductor substrate. A seed layer pattern filling a space between at least the two lower electrode patterns and having a planar surface is formed. A ferroelectric layer is formed on the lower electrode pattern and the seed layer pattern. An upper electrode overlapping the two lower electrode patterns is formed on the ferroelectric layer.

Abstract: Methods of forming a metal contact structure include forming an interlayer insulating layer on a substrate, etching the interlayer insulating layer to form a hole, depositing a metal layer on the surface of the interlayer insulating layer including inside the hole, planarizing the metal layer to provide a buried portion of the metal layer in the hole and to remove portions of the metal layer outside of the hole, etching-back the buried portion of the metal layer in the hole such that some of the portion of the metal layer within the hole remains and depositing a conductive layer on the surface of the interlayer insulating layer and the portion of the metal layer that remains within the hole. Methods of forming a phase change memory device are also provided.

Abstract: In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.

Abstract: A ferroelectric memory device includes a lower interlayer dielectric on a semiconductor substrate, a plurality of ferroelectric capacitors, and a plate line. The ferroelectric capacitors are on the lower interlayer dielectric. The plate line extends across and electrically connects to surfaces of at least two adjacent ones of the plurality of ferroelectric capacitors.

Abstract: A ferroelectric memory device includes an interlayer dielectric layer and a a protection adhesion layer formed thereon. A buried contact extends through the protection adhesion layer and the interlayer dielectric layer. A lower electrode is on a portion of the protection adhesion layer that is adjacent to the buried contact and on the buried contact. A ferroelectric layer covers the lower electrode and the protection adhesion layer. An upper electrode overlaps the lower electrode and covers the ferroelectric layer. Related methods are also disclosed.

Abstract: A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of rows and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes.

Abstract: A ferroelectric memory device includes an interlayer dielectric layer and a a protection adhesion layer formed thereon. A buried contact extends through the protection adhesion layer and the interlayer dielectric layer. A lower electrode is on a portion of the protection adhesion layer that is adjacent to the buried contact and on the buried contact. A ferroelectric layer covers the lower electrode and the protection adhesion layer. An upper electrode overlaps the lower electrode and covers the ferroelectric layer. Related methods are also disclosed.

Abstract: A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of rows and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes.

Abstract: A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of rows and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes.

Abstract: A ferroelectric memory device includes a lower interlayer dielectric on a semiconductor substrate, a plurality of ferroelectric capacitors, and a plate line. The ferroelectric capacitors are on the lower interlayer dielectric. The plate line extends across and electrically connects to surfaces of at least two adjacent ones of the plurality of ferroelectric capacitors.

Abstract: A ferroelectric memory device comprises an interlayer insulating layer and an adhesive layer over a semiconductor substrate. A storage node contact plug may extend through the adhesive layer and the interlayer insulating layer to connect a predetermined area of the semiconductor substrate. A ferroelectric capacitor may be connected to the storage node contact plug and on at least a portion of the adhesive layer.

Abstract: A method for manufacturing an electrode of a capacitor used in a semiconductor device, wherein a support insulating layer, an etch stop layer including a tantalum oxide layer, and a mold sacrificial insulating layer are sequentially formed on a semiconductor substrate. The mold sacrificial insulating layer, the etch stop layer and the support insulating layer are sequentially patterned to form a three-dimensional mold for a storage node. A storage node layer is formed to cover the inner surface of the mold. Next, storage nodes for capacitors are formed by dividing the storage node layer. The residual mold sacrificial insulating layer is removed by selectively wet etching, using the tantalum oxide layer as an etch stopper.

Abstract: A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of rows and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes.

Abstract: A capacitor of a semiconductor device which uses a high dielectric layer and a method of manufacturing the same are provided. The capacitor includes a storage electrode having at least two conductive patterns which overlap each other and a thermally-stable material layer pattern being positioned between the conductive layer patterns. The storage electrode and the thermally-stable material layer pattern are formed by alternately forming a conductive layer and a thermally-stable material layer, and patterning the conductive layer and the thermally-stable material layer to have predetermined shapes. With the present structure, it is possible to prevent the storage electrode from being transformed or broken during a thermal treatment process for forming a high dielectric layer on the storage electrode or in a subsequent high temperature thermal treatment process.

Abstract: A method for manufacturing an electrode of a capacitor used in a semiconductor device, wherein a support insulating layer, an etch stop layer including a tantalum oxide layer, and a mold sacrificial insulating layer are sequentially formed on a semiconductor substrate. The mold sacrificial insulating layer, the etch stop layer and the support insulating layer are sequentially patterned to form a three-dimensional mold for a storage node. A storage node layer is formed to cover the inner surface of the mold. Next, storage nodes for capacitors are formed by dividing the storage node layer. The residual mold sacrificial insulating layer is removed by selectively wet etching, using the tantalum oxide layer as an etch stopper.

Abstract: A method of forming a capacitor of a semiconductor device which can prevent disconnection between lower electrodes by blanket-depositing a second conductive film for silicidation on a semiconductor substrate and forming an oxide of the second conductive film such as titanium dioxide (TiO2) on an interlayer dielectric using high temperature oxidation, before depositing a dielectric film, and which can obtain a high capacitance by forming both a silicide layer including the second conductive film, and the oxide of the second conductive film such as titanium dioxide (TiO2) having a high dielectric constant, on a lower electrode, and using the silicide layer and oxide as the dielectric film.