Abstract: A semiconductor device includes a substrate, a gate feature, a gate spacer, and a dielectric layer. The gate feature is above the substrate and includes a gate electrode. The gate spacer is on a sidewall of the gate feature. The dielectric layer is in contact with the gate spacer and has a larger thickness than the gate electrode.

Abstract: A semiconductor device includes a substrate, a gate feature, a gate spacer, and a dielectric layer. The gate feature is above the substrate and includes a gate electrode. The gate spacer is on a sidewall of the gate feature. The dielectric layer is in contact with the gate spacer and has a larger thickness than the gate electrode.

Abstract: A method of manufacturing a bipolar-complementary metal oxide semiconductor (BiCMOS) is provided. A gate in a CMOS area and a conductive layer pattern defining an opening, which opens an active region in a bipolar transistor area, are simultaneously formed by patterning a gate conductive layer. Thereafter, bipolar transistor manufacturing processes are performed while CMOS manufacturing processes are performed. Accordingly, the number of masks is decreased, and degradation of device characteristics is prevented.

Abstract: A method of manufacturing a bipolar-complementary metal oxide semiconductor (BiCMOS) is provided. A gate in a CMOS area and a conductive layer pattern defining an opening, which opens an active region in a bipolar transistor area, are simultaneously formed by patterning a gate conductive layer. Thereafter, bipolar transistor manufacturing processes are performed while CMOS manufacturing processes are performed. Accordingly, the number of masks is decreased, and degradation of device characteristics is prevented.

Abstract: In a silicon-on-insulator (SOI) wafer and a method of manufacturing the same, the SOI wafer includes a first semiconductor wafer including an isolation insulating film formed to define an active region; a well region and a buried layer formed in the active region of the first semiconductor wafer; and a second semiconductor wafer bonded with the first semiconductor wafer, wherein an SOI insulating film, which contacts a lower portion of the isolation insulating film and electrically insulates a lower portion of the active region, is formed.

Abstract: Provided is a method for manufacturing a self-aligned BiCMOS including a SiGe heterojunction bipolar transistor (HBT) for performing high-frequency operations. In this method, an extrinsic base and a selective ion-implanted collector (SIC) are formed by a self-alignment process.

Abstract: Methods of making a paste of materials used in forming bumps for semiconductor applications wherein the distribution of trace elements is substantially uniform are provided. The methods of making a paste for a semiconductor package process comprises heating and fusing several materials to alloy the materials, rapidly cooling the fused alloy composition to improve conformity of the composition, processing the cooled alloy composition into a fine powder, and processing the alloy powder to be a paste-shape.

Abstract: Provided is a method for manufacturing a self-aligned BiCMOS including a SiGe heterojunction bipolar transistor (HBT) for performing high-frequency operations. In this method, an extrinsic base and a selective ion-implanted collector (SIC) are formed by a self-alignment process.

Abstract: In a silicon-on-insulator (SOI) wafer and a method of manufacturing the same, the SOI wafer includes a first semiconductor wafer including an isolation insulating film formed to define an active region; a well region and a buried layer formed in the active region of the first semiconductor wafer; and a second semiconductor wafer bonded with the first semiconductor wafer, wherein an SOI insulating film, which contacts a lower portion of the isolation insulating film and electrically insulates a lower portion of the active region, is formed.

Abstract: Methods of making a paste of materials used in forming bumps for semiconductor applications wherein the distribution of trace elements is substantially uniform are provided. The methods of making a paste for a semiconductor package process comprises heating and fusing several materials to alloy the materials, rapidly cooling the fused alloy composition to improve conformity of the composition, processing the cooled alloy composition into a fine powder, and processing the alloy powder to be a paste-shape.

Abstract: The present invention relates to a semiconductor device and a fabricating method therefor. According to the semiconductor device of the present invention, a phased layer of under bump metallurgy (UBM) is formed by repeatedly depositing chrome and copper layers with sputtering equipment in which chrome and copper targets are installed in singular or plural chambers. The chrome and copper layers of the phased layer are deposited in the structure of the same, thin multi-layers possible for mutual diffusion, wherein the chrome layers gradually get thinner and the copper layers gradually get thicker. As a consequence, reliability in the phased layer of the present invention is achieved with increase in the speed of depositing UBM to reduce the time and cost for all the fabricating processes of the semiconductor device.

Abstract: The present invention relates to a semiconductor device and a fabricating method therefor. According to the semiconductor device of the present invention, a phased layer of under bump metallurgy (UBM) is formed by repeatedly depositing chrome and copper layers with sputtering equipment in which chrome and copper targets are installed in singular or plural chambers. The chrome and copper layers of the phased layer are deposited in the structure of the same, thin multi-layers possible for mutual diffusion, wherein the chrome layers gradually get thinner and the copper layers gradually get thicker. As a consequence, reliability in the phased layer of the present invention is achieved with increase in the speed of depositing UBM to reduce the time and cost for all the fabricating processes of the semiconductor device.

Abstract: The present invention relates to a semiconductor device and a fabricating method therefor. According to the semiconductor device of the present invention, a phased layer of under bump metallurgy (UBM) is formed by repeatedly depositing chrome and copper layers with sputtering equipment in which chrome and copper targets are installed in singular or plural chambers. The chrome and copper layers of the phased layer are deposited in the structure of the same, thin multi-layers possible for mutual diffusion, wherein the chrome layers gradually get thinner and the copper layers gradually get thicker. As a consequence, reliability in the phased layer of the present invention is achieved with increase in the speed of depositing UBM to reduce the time and cost for all the fabricating processes of the semiconductor device.

Abstract: A manufacturing method of semiconductor devices in which sources and drains define effective channels having lengths which are essentially equal to target length is disclosed. The method includes the steps of forming a gate electrode on a semiconductor substrate, measuring a length of the gate electrode, calculating a lateral diffusion distance using the measured length of the gate electrode and a length of a target effective channel, determining implantation conditions for forming a source and drain having the lateral diffusion distance, and forming the source and drain, by ion implanting in accordance with the implantation conditions. Even though the length of the gate electrode is changed in accordance with a change of the process conditions, sources and drains defining effective channels of a target length can be formed.