Patents by Inventor Sang-Dong Kwon

Sang-Dong Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11947764
    Abstract: An input sensing unit includes a touch sensing unit, which includes a plurality of driving electrodes, a plurality of sensing electrodes, and a driving signal generating unit which provides driving signals to the driving electrodes. The sensing electrodes are insulated from and intersect the driving electrodes. The driving signal generating unit includes touch drivers connected to driving electrodes and a digital-to-analog converter configured to provide a first signal or a second signal, and each of the touch drivers is connected to a preset number of driving electrodes among the driving electrodes.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: April 2, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ji Woong Kim, Oh Jo Kwon, Kyung Tea Park, Keum Dong Jung, Sang Hyun Heo
  • Patent number: 10062550
    Abstract: Provided are substrate processing apparatuses including a temperature measurement unit. The substrate processing apparatus comprises a chamber including a substrate processing region, a dielectric sheet that is disposed on the substrate processing region and includes an insertion hole and a temperature measurement unit that is disposed on the dielectric sheet to measure the temperature of the dielectric sheet, and has a screw portion inserted into the insertion hole, wherein each of the insertion hole and the screw portion has thread helixes meshed with each other.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Pyo Hong, Kwang-Nam Kim, Sang-Dong Kwon, Jong-Woo Sun, Sang-Rok Oh, Yong-Moon Jang
  • Publication number: 20180053661
    Abstract: Disclosed are a plasma etching apparatus and a method of manufacturing semiconductor devices using the same. The plasma etching apparatus includes a process chamber. A source supplier is positioned at an upper portion of the process chamber. The source supplier is configured to supply source gases for an etching process. A substrate holder is positioned at a lower portion of the process chamber opposite to the source supplier. The substrate holder is configured to support a substrate. A first power source is configured to apply a high frequency power to capacitively couple the source gases into a capacitively coupled plasma (CCP) in the process chamber. A second power source is configured to apply a low frequency pulse power at a low duty ratio of less than or equal to about 0.5:1. The low frequency pulse power is configured to guide the CCP toward the substrate supported by the substrate holder.
    Type: Application
    Filed: February 27, 2017
    Publication date: February 22, 2018
    Inventors: MIN-JOON PARK, TAE-HWA KIM, JAE-HYUN LEE, SANG-DONG KWON
  • Publication number: 20170301578
    Abstract: A method of processing a substrate including loading the substrate into a plasma-processing apparatus. The plasma-processing apparatus includes a focus ring. The substrate is processed in the plasma-processing apparatus using plasma. The substrate is unloaded from the plasma-processing apparatus. A layer is formed on the focus ring. The layer is formed by an in-situ process in the plasma-processing apparatus.
    Type: Application
    Filed: January 3, 2017
    Publication date: October 19, 2017
    Inventors: Jung-Pyo HONG, Sang-Dong Kwon, Kwang-Nam Kim, Jong-Woo Sun, Sang-Rok Oh
  • Publication number: 20170062245
    Abstract: Provided are substrate processing apparatuses including a temperature measurement unit. The substrate processing apparatus comprises a chamber including a substrate processing region, a dielectric sheet that is disposed on the substrate processing region and includes an insertion hole and a temperature measurement unit that is disposed on the dielectric sheet to measure the temperature of the dielectric sheet, and has a screw portion inserted into the insertion hole, wherein each of the insertion hole and the screw portion has thread helixes meshed with each other.
    Type: Application
    Filed: April 29, 2016
    Publication date: March 2, 2017
    Inventors: Jung-Pyo Hong, Kwang-Nam KIM, Sang-Dong KWON, Jong-Woo SUN, Sang-Rok OH, Yong-Moon JANG
  • Publication number: 20090184391
    Abstract: Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.
    Type: Application
    Filed: March 10, 2009
    Publication date: July 23, 2009
    Inventors: Hyun-Chul Yoon, Jong-Kyu Kim, Jang-Bin Yim, Sang-Dong Kwon, Sung-Gil Choi
  • Patent number: 7510914
    Abstract: Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: March 31, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Chul Yoon, Jong-Kyu Kim, Jang-Bin Yim, Sang-Dong Kwon, Sung-Gil Choi
  • Publication number: 20070184694
    Abstract: Example embodiments relate to a wiring structure, a semiconductor device and methods of forming the wiring structure. The wiring structure may include a first contact plug, a second contact plug, a protecting layer pattern and an insulating structure. The first contact plug may be provided on a semiconductor substrate. The second contact plug may be provided on the first contact plug to be electrically connected to the first contact plug. The protecting layer pattern may encompass an upper sidewall of the first contact plug and a sidewall of the second contact plug to retard chemicals from infiltrating into an interface between the first and second contact plugs. The insulating structure may encompass the first contact plug, the second contact plug and the protecting layer pattern.
    Type: Application
    Filed: November 3, 2006
    Publication date: August 9, 2007
    Inventors: Jong-Kyu Kim, Jong-Chul Park, Jang-Bin Yim, Sang-Dong Kwon, Ki-Jeong Kim, Sung-Gil Choi
  • Publication number: 20070066056
    Abstract: Example embodiments of the present invention provide a method of removing a photoresist and a method of manufacturing a semiconductor device using the same. In a method of removing a photoresist and a method of manufacturing a semiconductor device, a plasma including active ions and radicals may be generated. The active ions may be modified into directional active ions. The photoresist may be etched using the directional active ions as main etching factors and/or the radicals as subsidiary etching factors. The photoresist may be completely removed from the semiconductor device such as a lower electrode. Thus, the likelihood of an increase in electrical resistance due to residual photoresist may decrease.
    Type: Application
    Filed: June 6, 2006
    Publication date: March 22, 2007
    Inventors: Jong-Kyu Kim, Sung-Gil Choi, Jang-Bin Yim, Sang-Dong Kwon, Ki-Jeong Kim
  • Publication number: 20060289899
    Abstract: Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.
    Type: Application
    Filed: June 7, 2006
    Publication date: December 28, 2006
    Inventors: Hyun-Chul Yoon, Jong-Kyu Kim, Jang-Bin Yim, Sang-Dong Kwon, Sung-Gil Choi