Abstract: A physically unclonable device according to an embodiment of the present disclosure comprises: a plurality of inverters disposed on a first path to which a first signal is input; a plurality of inverters disposed on a second path to which a second signal is input; a first MOS capacitor disposed on the first path; and a second MOS capacitor disposed on the second path, wherein a first voltage is applied to a MOS capacitor located on the path corresponding to whichever of the first signal or the second signal arrives later at an output terminal of the first path or an outer terminal of the second path. Accordingly, a physically unclonable device that does not require separate error correction can be achieved.