Patents by Inventor Sang-Geun Koo
Sang-Geun Koo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136276Abstract: A semiconductor device includes a bottom metal line and a bottom electrode disposed on a substrate, a thick inter-metal dielectric layer disposed on the bottom metal line and the bottom electrode, a first via disposed on the bottom metal line disposed in the thick inter-metal dielectric layer, a second via disposed on the first via, a top metal line disposed on the second via and overlapping the bottom metal line, a low bandgap dielectric layer disposed on the thick inter-metal dielectric layer, a hard mask layer disposed on the low bandgap dielectric layer, a top electrode disposed on the hard mask layer and overlapping the bottom electrode, and a passivation layer disposed on the top metal line and the top electrode.Type: ApplicationFiled: April 11, 2023Publication date: April 25, 2024Applicant: KEY FOUNDRY CO., LTD.Inventors: Jong Yeul JEONG, Sang Geun KOO, Jeong Ho SHEEN, Kang Sup SHIN
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Publication number: 20240063112Abstract: A semiconductor device including a high-voltage isolation capacitor and a mixed-signal integrated circuit, wherein the high-voltage isolation capacitor includes bottom electrodes, each spaced apart from another, disposed on a substrate; top electrodes disposed on corresponding ones of the bottom electrodes; an inter-metal dielectric layer disposed between the bottom electrodes and the top electrodes; and low bandgap dielectric layers disposed on the inter-metal dielectric layer. Each of the low bandgap dielectric layers is disposed below corresponding ones of the top electrodes, and the low bandgap dielectric layers are absent in the mixed-signal integrated circuit.Type: ApplicationFiled: March 23, 2023Publication date: February 22, 2024Applicant: KEY FOUNDRY CO., LTD.Inventors: Jong Yeul JEONG, Jeong Ho SHEEN, Sang Geun KOO, Kang Sup SHIN
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Publication number: 20240063111Abstract: A method for manufacturing a semiconductor device is provided. The method includes providing a high-voltage isolation capacitor region and a mixed-signal integrated circuit region on a substrate, forming a bottom electrode on the high-voltage isolation capacitor region, forming a bottom metal line on the mixed-signal integrated circuit region, forming an inter-metal dielectric layer on the bottom electrode and the bottom metal line, forming a top via in the inter-metal dielectric layer, forming a low bandgap dielectric layer on the top via and the inter-metal dielectric layer, patterning the low bandgap dielectric layer to form a patterned low bandgap dielectric layer, depositing a thick metal film on the top via and the patterned low bandgap dielectric layer, and patterning the thick metal film to form a top metal line on the high-voltage isolation capacitor region and form a top electrode on the mixed-signal integrated circuit region.Type: ApplicationFiled: March 2, 2023Publication date: February 22, 2024Applicant: KEY FOUNDRY CO., LTD.Inventors: Jong Yeul JEONG, Jeong Ho SHEEN, Sang Geun KOO, Kang Sup SHIN
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Publication number: 20230070272Abstract: A semiconductor device is provided. The semiconductor device includes a logic region and a capacitor region, wherein the capacitor region comprises a bottom electrode disposed on a substrate; a top electrode disposed on the bottom electrode; a first inter-metal dielectric film disposed between the substrate and the bottom electrode; a second inter-metal dielectric film and a third inter-metal dielectric film disposed between the top electrode and the bottom electrode; a passivation film disposed on the top electrode, wherein the top electrode is configured to have a rounded top corner, and the bottom electrode is configured to have a sharp top corner.Type: ApplicationFiled: February 11, 2022Publication date: March 9, 2023Applicant: KEY FOUNDRY CO., LTD.Inventors: Sang Geun KOO, Jong Yeul JEONG
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Publication number: 20170138882Abstract: Provided is a capacitive humidity sensor. The capacitive humidity sensor includes an upper electrode disposed on a first plane, a plurality of first electrodes included in the upper electrode, a plurality of second electrodes disposed between the first electrodes, and a humidity sensitive layer surrounding the second electrodes.Type: ApplicationFiled: January 30, 2017Publication date: May 18, 2017Applicant: Magnachip Semiconductor, Ltd.Inventors: Sang Geun KOO, Kwan Soo KIM
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Patent number: 9594041Abstract: Provided is a capacitive humidity sensor. The capacitive humidity sensor includes an upper electrode disposed on a first plane, a plurality of first electrodes included in the upper electrode, a plurality of second electrodes disposed between the first electrodes, and a humidity sensitive layer surrounding the second electrodes.Type: GrantFiled: February 24, 2014Date of Patent: March 14, 2017Assignee: Magnachip Semiconductor, Ltd.Inventors: Sang Geun Koo, Kwan Soo Kim
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Publication number: 20150068302Abstract: Provided is a capacitive humidity sensor. The capacitive humidity sensor includes an upper electrode disposed on a first plane, a plurality of first electrodes included in the upper electrode, a plurality of second electrodes disposed between the first electrodes, and a humidity sensitive layer surrounding the second electrodes.Type: ApplicationFiled: February 24, 2014Publication date: March 12, 2015Applicant: MagnaChip Semiconductor, Ltd.Inventors: Sang Geun KOO, Kwan Soo KIM
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Patent number: 8530323Abstract: A method for fabricating a capacitor is provided. The method for fabricating a capacitor includes forming a dielectric layer over a lower electrode on a substrate, forming an upper electrode over the dielectric layer, forming a hard mask over the upper electrode, etching the hard mask to form a hard mask pattern, etching the upper electrode to make the dielectric layer remain on the lower electrode in a predetermined thickness, forming an isolation layer along an upper surface of the remaining dielectric layer and the hard mask pattern, leaving the isolation layer having a shape of a spacer on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer, and etching the lower electrode to be isolated.Type: GrantFiled: March 9, 2012Date of Patent: September 10, 2013Assignee: Magnachip Semiconductor, Ltd.Inventors: Jin-Youn Cho, Young-Soo Kang, Jong-Il Kim, Sang-Geun Koo
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Patent number: 8445991Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a lower electrode formed on a substrate, a dielectric layer including an etched dielectric region and an as-grown dielectric region formed on the lower electrode, an upper electrode formed on the as-grown dielectric region, a hardmask formed on the upper electrode, a spacer formed at a side surface of the hardmask and the upper electrode and over a surface of the etched dielectric region, and a buffer insulation layer formed on the hardmask and the spacer.Type: GrantFiled: January 6, 2011Date of Patent: May 21, 2013Assignee: Magnachip Semiconductor, Ltd.Inventors: Jin-Youn Cho, Young-soo Kang, Sang-Geun Koo
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Publication number: 20120171840Abstract: A method for fabricating a capacitor is provided. The method for fabricating a capacitor includes forming a dielectric layer over a lower electrode on a substrate, forming an upper electrode over the dielectric layer, forming a hard mask over the upper electrode, etching the hard mask to form a hard mask pattern, etching the upper electrode to make the dielectric layer remain on the lower electrode in a predetermined thickness, forming an isolation layer along an upper surface of the remaining dielectric layer and the hard mask pattern, leaving the isolation layer having a shape of a spacer on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer, and etching the lower electrode to be isolated.Type: ApplicationFiled: March 9, 2012Publication date: July 5, 2012Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Jin-Youn Cho, Young-Soo Kang, Jong-Il Kim, Sang-Geun Koo
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Patent number: 8159046Abstract: A capacitor includes a lower electrode; a dielectric layer formed on a predetermined portion of the lower electrode; an upper electrode formed on the dielectric layer; a hard mask pattern formed on the upper electrode; and an isolation layer having a shape of a spacer, formed on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer.Type: GrantFiled: October 21, 2009Date of Patent: April 17, 2012Assignee: Magnachip Semiconductor, Ltd.Inventors: Jin-Youn Cho, Young-Soo Kang, Jong-Il Kim, Sang-Geun Koo
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Publication number: 20110108951Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a lower electrode formed on a substrate, a dielectric layer including an etched dielectric region and an as-grown dielectric region formed on the lower electrode, an upper electrode formed on the as-grown dielectric region, a hardmask formed on the upper electrode, a spacer formed at a side surface of the hardmask and the upper electrode and over a surface of the etched dielectric region, and a buffer insulation layer formed on the hardmask and the spacer.Type: ApplicationFiled: January 6, 2011Publication date: May 12, 2011Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Jin-Youn CHO, Young-Soo Kang, Sang-Geun Koo
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Publication number: 20100155889Abstract: A capacitor includes a lower electrode; a dielectric layer formed on a predetermined portion of the lower electrode; an upper electrode formed on the dielectric layer; a hard mask pattern formed on the upper electrode; and an isolation layer having a shape of a spacer, formed on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer.Type: ApplicationFiled: October 21, 2009Publication date: June 24, 2010Inventors: Jin-Youn CHO, Young-Soo Kang, Jong-Il Kim, Sang-Geun Koo