Abstract: A memory cell includes a metal oxide semiconductor (MOS) capacitor including a gate coupled to a storage node and an electrode coupled to a synchronization control line. The MOS capacitor adds a coupling voltage to the gate based on a change in voltage on the synchronization control line. The coupling voltage may maintain the storage node within a predetermined range.

Abstract: A memory cell includes a metal oxide semiconductor (MOS) capacitor including a gate coupled to a storage node and an electrode coupled to a synchronization control line. The MOS capacitor adds a coupling voltage to the gate based on a change in voltage on the synchronization control line. The coupling voltage may maintain the storage node within a predetermined range.

Abstract: A semiconductor device includes a fuse part including an antifuse that is connected between a first common node to which a high voltage that is higher than an internal boost voltage is applied and a first node. The fuse part is enabled in response to a program mode selection signal and an address signal so as to fuse the antifuse in response to the high voltage applied to the first common node and to set a voltage level of a second node. A latch circuit is configured to latch an output signal responsive to the voltage level of the second node when the fuse part is in a fused state. A protection circuit is configured to lower a voltage level at the first node when the fuse part is not enabled and the high voltage is applied to the first common node.

Abstract: A semiconductor device includes a fuse part including an antifuse that is connected between a first common node to which a high voltage that is higher than an internal boost voltage is applied and a first node. The fuse part is enabled in response to a program mode selection signal and an address signal so as to fuse the antifuse in response to the high voltage applied to the first common node and to set a voltage level of a second node. A latch circuit is configured to latch an output signal responsive to the voltage level of the second node when the fuse part is in a fused state. A protection circuit is configured to lower a voltage level at the first node when the fuse part is not enabled and the high voltage is applied to the first common node.

Abstract: A method of fabricating a semiconductor device, includes the steps of forming gates in a cell region and in a peripheral region of a substrate, forming a polysilicon layer over an entire surface of the resultant structure, partially removing portions of the polysilicon layer in the cell region to maintain the polysilicon layer of a predetermined thickness in the cell region, removing the predetermined thickness of the polysilicon layer both in the cell and peripheral regions, so that the resultant structure includes exposed gates in the cell region but no exposed gates in the peripheral region, and forming an insulating layer over the resultant structure.

Abstract: A method of fabricating a semiconductor device, includes the steps of forming gates in a cell region and in a peripheral region of a substrate, forming a polysilicon layer over an entire surface of the resultant structure, partially removing portions of the polysilicon layer in the cell region to maintain the polysilicon layer of a predetermined thickness in the cell region, removing the predetermined thickness of the polysilicon layer both in the cell and peripheral regions, so that the resultant structure includes exposed gates in the cell region but no exposed gates in the peripheral region, and forming an insulating layer over the resultant structure.

Abstract: A capacitor includes a substrate, an insulating layer on the substrate, the insulating layer having a contact hole, a first storage node in the contact hole and on the insulating layer, a second storage node on a peripheral portion of the first storage node, the second storage node having a planar top surface, a dielectric layer on the surface of the first and second storage nodes, and a plate node on the dielectric layer.

Abstract: A semiconductor device includes a substrate having an active region between field oxide films, a gate formed on the substrate with a gate oxide therebetween, and a first impurity region formed adjacent to each side of the gate. A second impurity region is formed between the field oxide film and the first impurity region and a first insulating film with a contact hole exposes portions of the first and second impurity regions. An electrode formed in the contact hole such that the portions of the first and second impurity regions overlap an area in the substrate beneath the electrode.

Abstract: A method for manufacturing a semiconductor device, the method includes the steps of forming an n-type well and a p-type well under a surface of a semiconductor substrate, forming a pad oxide layer having a first thickness on the p-type well and a second thickness on the n-type well, the first thickness being greater than the second thickness, and forming a field oxide layer between the n-type well and the p-type well, the field oxide layer having less bird's beak on the n-type well than on the p-type well.

Abstract: A capacitor includes a substrate having a first trench, and a second trench, a first storage node having a first body and a first flange, the first body being on the first trench and having a first height and the first flange being extended at a top portion of the first body to a first length from the first body, a second storage node having a second body and a second flange, the second body being in the second trench and having a second height different from the first height of the first body, and the second flange being extended in a direction opposite to the first flange to a second length from the second length from the second body, a dielectric film on the surfaces of the first and second storage nodes, and a plate electrode on the dielectric film.