Abstract: A semiconductor device includes a plurality of memory cells, and a peripheral circuit configured to control the plurality of memory cells. The peripheral circuit includes a temperature compensation circuit configured to output a compensation current determined based on a temperature of the semiconductor device, a voltage regulator configured to regulate a pump voltage having a level determined based on the compensation current, a clock generator configured to generate a clock signal having a frequency determined based on the compensation current; and a charge pump circuit including a level shifter, configured to output a control signal adjusted a swing level of the control signal based on the clock signal and the pump voltage, and a plurality of unit circuits, each of the plurality of unit circuits including a plurality of pumping capacitors configured to be charged and discharged by the control signal.

Abstract: Provided a voltage generating circuits including assist circuits and operating methods thereof. The voltage generating circuit which includes an assist circuit that generates an assist signal indicating an enable mode or a disable mode. When a first power supply voltage is lower than an assist reference voltage, the assist signal indicates the enable mode, and a compensation circuit generates a compensation signal based on the first power supply voltage. An internal voltage converter generates a regulated voltage based on the first power supply voltage, and a charge pump circuit generates a pump voltage based on the regulated voltage. The compensation signal compensates for the regulated voltage.

Abstract: A memory device includes a memory cell array, a voltage switching circuit configured to switch a plurality of voltages provided to the memory cell array in response to a switching control signal, a discharge circuit configured to discharge the voltage switching circuit in response to a discharge signal, and a control circuit configured to generate the switching control signal based on a command and a high voltage enable signal received from outside of the memory device. The voltage switching circuit includes a high voltage switching circuit, and a low voltage switching circuit. The control circuit is configured to generate the discharge signal based on the command and an activated high voltage enable signal responsive to detecting external abortion while performing an operation corresponding to the command from among a program operation and an erase operation.

Abstract: Provided a voltage generating circuits including assist circuits and operating methods thereof. The voltage generating circuit which includes an assist circuit that generates an assist signal indicating an enable mode or a disable mode. When a first power supply voltage is lower than an assist reference voltage, the assist signal indicates the enable mode, and a compensation circuit generates a compensation signal based on the first power supply voltage. An internal voltage converter generates a regulated voltage based on the first power supply voltage, and a charge pump circuit generates a pump voltage based on the regulated voltage. The compensation signal compensates for the regulated voltage.

Abstract: A memory device includes a memory cell array, a voltage switching circuit configured to switch a plurality of voltages provided to the memory cell array in response to a switching control signal, a discharge circuit configured to discharge the voltage switching circuit in response to a discharge signal, and a control circuit configured to generate the switching control signal based on a command and a high voltage enable signal received from outside of the memory device. The voltage switching circuit includes a high voltage switching circuit, and a low voltage switching circuit. The control circuit is configured to generate the discharge signal based on the command and an activated high voltage enable signal responsive to detecting external abortion while performing an operation corresponding to the command from among a program operation and an erase operation.