Abstract: A wire-wound inductor includes: a magnetic core; a first coil unit embedded in the magnetic core and formed by winding a conductive wire; a pair of second coil units bent from both ends of the first coil unit and including lead portions exposed to opposing surfaces of the magnetic core; and a pair of external terminals disposed on the opposing surfaces of the magnetic core and electrically connected to the lead portions of the pair of second coil units, respectively.

Abstract: A coil component includes a core including a winding portion and a flange portion extending from a first end of the winding portion, a coil wound around the winding portion, a lead formed at the flange portion, and a cover coupled to the flange portion and covering at least a portion of the coil.

Abstract: A memory chip includes a chip input-output pad unit, a plurality of semiconductor dies. The chip input-output pad unit includes a plurality of input-output pins connected to an external device and the plurality of semiconductor dies are connected commonly to the chip input-output pad unit and having a full memory capacity respectively. Each semiconductor die includes a die input-output pad unit, a memory region and a conversion block. The die input-output pad unit includes a plurality of input-output terminals respectively connected to the input-output pins of the chip input-output pad unit. The memory region includes an activated region corresponding to a portion of the full memory capacity and a deactivated region corresponding to a remainder portion of the full memory capacity. The conversion block connects the activated region except the deactivated region to the die input-output pad unit.

Abstract: A semiconductor memory device includes a cell array and a refresh controller coupled to the cell array. The refresh controller is configured to insert at least one insertion refresh address in a first refresh address sequence based on address information about the cell array to generate a second refresh address sequence and to apply the second refresh address sequence to the cell array, such that selected cells may be refreshed more frequently without increasing an overall refresh rate.

Abstract: An electronic component includes a coil including lead terminals plated with a metal; a body part filling a space around the coil; and external electrodes connected to the lead terminals of the coil. At least portions of the lead terminals of the coil are exposed externally of the body part.

Abstract: A memory device to correct a defect cell generated after packing is performed includes a memory cell array in which a plurality of memory cells are arranged, a repair circuit unit including a first storage unit to store defect cell information in the memory cell array, and a fuse circuit unit including a second storage unit that is programmed according to the defect cell information stored in the first storage unit. The first storage unit includes a volatile memory device, and the second storage unit includes a non-volatile memory device.

Abstract: A terminal, a cloud apparatus, a method of analyzing, by a terminal, activities of a user, and a method of analyzing, by a cloud apparatus, activities of a user. The terminal includes a communication interface that communicates with an external apparatus over a network; a controller that obtains data used to predict activities of a user and anonymize a portion of the obtained data, and transmit the anonymized data and a remaining portion of the data, which is not anonymized, to the external apparatus through the communication interface; and a display that displays notification information related to the activities of the user based on activity prediction data received from the external apparatus, the activity prediction data being generated based on an analysis of the transmitted data.

Abstract: A wire-wound inductor includes: a magnetic core; a first coil unit embedded in the magnetic core and formed by winding a conductive wire; a pair of second coil units bent from both ends of the first coil unit and including lead portions exposed to opposing surfaces of the magnetic core; and a pair of external terminals disposed on the opposing surfaces of the magnetic core and electrically connected to the lead portions of the pair of second coil units, respectively.

Abstract: A semiconductor memory device includes: a memory unit including a first memory sub region including a first memory cell and a second memory sub region including a second memory cell; a temperature information obtaining unit that obtains temperature information; a temperature estimation unit that estimates a first temperature of the first memory sub region and a second temperature of the second memory sub region based on the temperature information; a first sub region control unit that controls the first memory sub region based on the first temperature; and a second sub region control unit that controls the second memory sub region based on the second temperature.

Abstract: A memory chip includes a chip input-output pad unit, a plurality of semiconductor dies. The chip input-output pad unit includes a plurality of input-output pins connected to an external device and the plurality of semiconductor dies are connected commonly to the chip input-output pad unit and having a full memory capacity respectively. Each semiconductor die includes a die input-output pad unit, a memory region and a conversion block. The die input-output pad unit includes a plurality of input-output terminals respectively connected to the input-output pins of the chip input-output pad unit. The memory region includes an activated region corresponding to a portion of the full memory capacity and a deactivated region corresponding to a remainder portion of the full memory capacity. The conversion block connects the activated region except the deactivated region to the die input-output pad unit.

Abstract: An electronic apparatus includes a communication unit connected to a first unit network and configured for communication with a plurality of unit networks comprising a plurality of clients, and a controller configured to control the electronic apparatus within the first unit network to operate in one of a proxy mode and a node mode if the plurality of clients form a private network, wherein the controller controls the electronic apparatus to directly communicate with a second unit network in the proxy mode, and controls the electronic apparatus to be connected to another client of the first unit network operating in the proxy mode and communicate with the second unit network through the other client in the node mode, and when the electronic apparatus operates in the node mode, the controller selectively changes the operational mode to the proxy mode depending on a private network service provided to the electronic apparatus.

Abstract: Disclosed herein are an inductor and a manufacturing method thereof. The manufacturing method of an inductor includes: positioning a printed circuit board (PCB) including a predetermined pattern formed thereon and an insertion part formed at one side thereof; fixing a protrusion part formed at a lower portion of a core so as to be inserted into the insertion part; electrically connecting both ends of a coil wound around the core to a lower PCB terminal disposed at a lower portion of the PCB, respectively; and forming an appearance so that the core, the coil, and an upper exposed surface of the PCB are received therein.

Abstract: The present disclosure relates to an apparatus and method capable of carrying out data movement in a memory of a terminal. The apparatus includes a processor configured to transmit a command for data movement and address information for data movement in a memory to the memory, and the memory configured to perform the data movement in units of word line in the memory by using the address information, in response to reception of the command for moving the data.

Abstract: A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

Abstract: The present invention relates to an acrylic artificial marble having a granite pattern and a method of manufacturing the same, which can provide a natural marble effect by mixing and molding two or more compounds having different colors and thus can obtain a granite pattern in which patterns of the two or more compounds are smoothly mixed, and which can obtain a desired pattern remarkably similar to a pattern of natural stone by using a multicolor chip sheet.

Abstract: A refresh circuit and a semiconductor memory device including the refresh circuit are disclosed. The refresh circuit includes a mode register, a refresh controller and a multiplexer circuit. The mode register generates a mode register signal having information relating to a memory bank on which a refresh operation is to be performed. The refresh controller generates a self-refresh active command and a self-refresh address based on a self-refresh command and an oscillation signal. The multiplexer circuit may include a plurality of multiplexers. Each of the multiplexers selects one of an active command and the self-refresh active command in response to bits of the mode register signal. Each of the multiplexers generates a row active signal based on the selected command, and selects one of an external address and the self-refresh address to generate a row address.

Abstract: A memory device includes an anti-fuse cell array including a plurality of anti-fuse cells. Each anti-fuse cell includes a first cell transistor connected to a common node, a second cell transistor connected to the common node, and an access transistor connected to the common node. The first cell transistor is configured to store data and the second cell transistor is configured to store data when the first cell transistor has defect data.

Abstract: A semiconductor memory device includes: a memory unit including a first memory sub region including a first memory cell and a second memory sub region including a second memory cell; a temperature information obtaining unit that obtains temperature information; a temperature estimation unit that estimates a first temperature of the first memory sub region and a second temperature of the second memory sub region based on the temperature information; a first sub region control unit that controls the first memory sub region based on the first temperature; and a second sub region control unit that controls the second memory sub region based on the second temperature.

Abstract: Disclosed herein is a method of manufacturing a coil, including: preparing a mold having vertically movable fixing pins disposed therein and slidable left and right sidewalls; seating a magnetic plate on an inner bottom of the mold; loading the coil on the magnetic plate so that lead parts of the coil are disposed between the fixing pins and the sidewalls of the mold; sliding the left and right sidewalls of the mold into the mold to closely adhere the lead parts of the coil to the fixing pins; filling a magnetic slurry in the mold and primarily pressing the magnetic slurry; and lowering the fixing pins to perform secondary pressing, in order to prevent deformation or position deviation of the coil at the time of molding the coil.

Abstract: Disclosed herein are an inductor and a manufacturing method thereof. The manufacturing method of an inductor includes: positioning a printed circuit board (PCB) including a predetermined pattern formed thereon and an insertion part formed at one side thereof; fixing a protrusion part formed at a lower portion of a core so as to be inserted into the insertion part; electrically connecting both ends of a coil wound around the core to a lower PCB terminal disposed at a lower portion of the PCB, respectively; and forming an appearance so that the core, the coil, and an upper exposed surface of the PCB are received therein.