Abstract: A computing resource management system using software modularization in a cluster computing environment in which computing devices are connected, including an application process running on each computing device and an algorithm processing process configured to run independently of the application process and perform task processing on the application process, the computing resource management system including: a task managing system configured to receive a task request message from an application process requiring a task from each computing device; a process managing system configured to confirm an algorithm processing process of computing devices connected to the cluster computing environment, and determine whether there is an algorithm processing process in an idle state to which the application process requested for a task will be assigned; and a performed managing system configured to confirm a result of an application process whose task is performed by the algorithm processing process.

Abstract: A docking control system for a vehicle and a building and a method therefor, includes a plurality of sensors including a vehicle sensor and a gate sensor, and a controller, when a vehicle approaches a gate, which controls the plurality of sensors to set amount of movement of the vehicle, to move the gate so that a vehicle door and the gate are brought into close contact with each other, and when positional satisfaction between the vehicle door and the gate is achieved, which opens the vehicle door and the gate so that an indoor space of the vehicle and an indoor space of the building are connected each other into one space.

Abstract: The inventive concept provides a teaching method for teaching a transfer position of a transfer robot. The teaching method includes: searching for an object on which a target object to be transferred by the transfer robot is placed, based on a 3D position information acquired by a first sensor; and acquiring coordinates of a second direction and coordinates of a third direction of the object based on a data acquired from a second sensor which is a different type from the first sensor.

Abstract: A conductive composite material, a method of preparing the same, and a secondary battery including the same. The conductive composite material may increase the proportion of an active material when forming an electrode by chemically bonding a conductive material and a binder to each other. A method of preparing the conductive composite material comprises ionizing carbon-based particles in a predetermined polarity, ionizing PTFE particles in a polarity different from that of the carbon-based particles, and chemically bonding the ionized carbon-based particles and the ionized PTFE particles, which are ionized in different polarities, to each other.

Abstract: A vehicle body frame includes a lower frame fixed to a floor of a vehicle to define a lower region of an internal space in the vehicle, a roof frame connected to an upper portion of the lower frame to define an upper region of the internal space, configured to slid in a vertical direction of the vehicle with respect to the lower frame, to expand the internal space upwards when the roof frame slides upwards, a lower door frame forming a lower portion of a vehicle door, and an upper door frame connected to the lower door frame to form an upper portion of the vehicle door, and configured to slid together with the roof frame to expand the vehicle door upwards when the roof frame slides upwards.

Abstract: An apparatus for predicting a traffic speed and a method thereof are provided. The apparatus includes an input device that receives traffic speed sequences of a plurality of links and a controller that detects a spatio-temporal relationship between traffic speeds of the plurality of links and predicts a future traffic speed of a target link based on the spatio-temporal relationship between the traffic speeds of the plurality of links.

Abstract: Provided is a display device comprising a substrate, a first data line and a second data line disposed on the substrate and extended in a first direction, an anode electrode disposed on the first data line and the second data line, a pixel-defining film disposed over the anode electrode and defining an emission area, an organic light-emitting layer disposed on the anode electrode, and a cathode electrode disposed on the organic light-emitting layer, wherein each of the first data line and the second data line has a curved shape when viewed from a top where the first anode electrode and the second anode electrode overlap the anode electrode.

Abstract: A positive electrode material for a lithium secondary battery has improved electron conductivity and surface stability because oxidation-treated carbon nanotubes are stably attached to the surface of an active material. According to one embodiment the positive electrode material includes a positive electrode active material core made of a Li—Ni—Co—Mn-M-O-based material (M=transition metal) and an oxidized carbon nanotube coating layer formed on the surface of the positive electrode active material core and including 1% to 3% by weight of oxidation-treated carbon nanotubes (OCNT) relative to 100% by weight of the positive electrode active material core.

Abstract: A positive electrode material for a lithium secondary battery and a manufacturing method therefor are provided. The positive electrode material may have carbon nanotubes stably attached to a surface of an active material and may exhibit increased electron conductivity and improved surface stability. The positive electrode material for a lithium secondary battery may comprises: a positive electrode active material core comprising a Li—Ni—Co—Mn-M-O-based material, where M is a transition metal; and a carbon nanotube coating layer on a surface of the positive electrode active material core. Carbon nanotubes (CNT) may be in an amount of 1-5 wt %, based on 100 wt % of the positive electrode active material core.

Abstract: A display device includes a light emitting element including a pixel electrode, a light emitting layer, and a common electrode. A capping layer is disposed on the common electrode. An auxiliary layer is disposed on the capping layer. A thin film encapsulation layer includes a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer includes a first inorganic insulating layer including silicon nitride; a second inorganic insulating layer including silicon oxide; and a third inorganic insulating layer including silicon oxynitride. The auxiliary layer has a thickness of 200 ? to 1400 ?, the first inorganic insulating layer has a thickness of 400 ? to 3500 ?, the second inorganic insulating layer has a thickness of 200 ? to 2400 ?, and the third inorganic insulating layer has a thickness of 4000 ? or more.

Abstract: A method of monitoring a semiconductor fabrication process including forming a barrier pattern on a substrate, forming a sacrificial pattern on the barrier pattern, removing the sacrificial pattern to expose a surface of the barrier pattern, generating photoelectrons by irradiating X-rays to a surface of the substrate, and inferring at least one material existing on the surface of the substrate by collecting and analyzing the photoelectrons may be provided.

Abstract: According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

Abstract: According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

Abstract: A method for fabricating a capacitor of a semiconductor device, and a capacitor made in accordance with the method, wherein the method includes forming a plate electrode polysilicon layer on a semiconductor substrate having a cell array region and a core/peripheral circuit region. The plate electrode polysilicon layer in the cell array region is patterned to form an opening, wherein the inner wall of the opening is used as a plate electrode. After forming a dielectric layer in the opening, a storage node is formed as a spacer on the dielectric layer on the inner wall of the opening. The plate electrode polysilicon layer in the core/peripheral circuit region remains to provide the same height between the cell array region where the cell capacitor is formed and the core/peripheral circuit region.

Abstract: An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

Abstract: An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

Abstract: A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact by employing a predefined plate silicon layer and forming a capacitor dielectric using the storage contact node, as a result, it becomes possible to resolve “lift-off” problems, twin-bit failures, and misalignment.

Abstract: An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

Abstract: A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact by employing a predefined plate silicon layer and forming a capacitor dielectric using the storage contact node, as a result, it becomes possible to resolve “lift-off” problems, twin-bit failures, and misalignment.

Abstract: A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact by employing a predefined plate silicon layer and forming a capacitor dielectric using the storage contact node, as a result, it becomes possible to resolve “lift-off” problems, twin-bit failures, and misalignment.