Patents by Inventor Sang Hoan Chang
Sang Hoan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230196753Abstract: An object recognition device including an artificial neural network (NN) engine configured to receive learning data and weights, make an object recognition model (ORM) learn by using the received information, and provide selected weight data including weights from the selected portion of the weights, and further configured to receive a feature vector, and apply the feature vector extracted from an object data that constructs the object and the selected weight data to the learned ORM to provide an object recognition result, a nonvolatile memory (NVM) configured to store the learned ORM, and an error correction code (ECC) engine configured to perform an ECC encoding on the selected weight data to generate parity data, provide the selected weight data and the parity data to the NVM, and provide the selected weight data to the NN engine by performing an ECC decoding on the selected weight data based on the parity data.Type: ApplicationFiled: February 20, 2023Publication date: June 22, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Eun-Jin YUN, Sung-Joon Kim, Sang-Hoan Chang
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Patent number: 11586848Abstract: An object recognition device including an artificial neural network (NN) engine configured to receive learning data and weights, make an object recognition model (ORM) learn by using the received information, and provide selected weight data including weights from the selected portion of the weights, and further configured to receive a feature vector, and apply the feature vector extracted from an object data that constructs the object and the selected weight data to the learned ORM to provide an object recognition result, a nonvolatile memory (NVM) configured to store the learned ORM, and an error correction code (ECC) engine configured to perform an ECC encoding on the selected weight data to generate parity data, provide the selected weight data and the parity data to the NVM, and provide the selected weight data to the NN engine by performing an ECC decoding on the selected weight data based on the parity data.Type: GrantFiled: February 6, 2019Date of Patent: February 21, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Jin Yun, Sung-Joon Kim, Sang-Hoan Chang
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Patent number: 10672479Abstract: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines; a calculation circuit configured to perform a calculation on information bits and weight bits based on a calculation window having a first size, the information bits and weight bits being included in a user data set, the memory cell array being configured to store the user data set, the calculation circuit being further configured to receive the user data set through the page buffer circuit; and a data input/output (I/O) circuit connected to the calculation circuit, wherein the calculation circuit is further configured to provide an output data set to the data I/O circuit in response to the calculation circuit completing the calculation with respect to all of the information bits and the weight bits, and wherein the output data set corresponds to a result of the completed calculation.Type: GrantFiled: September 11, 2018Date of Patent: June 2, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taek-Soo Kim, Chan-Ik Park, Hyun-Sung Shin, Sang-Hoan Chang
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Publication number: 20200034666Abstract: An object recognition device including an artificial neural network (NN) engine configured to receive learning data and weights, make an object recognition model (ORM) learn by using the received information, and provide selected weight data including weights from the selected portion of the weights, and further configured to receive a feature vector, and apply the feature vector extracted from an object data that constructs the object and the selected weight data to the learned ORM to provide an object recognition result, a nonvolatile memory (NVM) configured to store the learned ORM, and an error correction code (ECC) engine configured to perform an ECC encoding on the selected weight data to generate parity data, provide the selected weight data and the parity data to the NVM, and provide the selected weight data to the NN engine by performing an ECC decoding on the selected weight data based on the parity data.Type: ApplicationFiled: February 6, 2019Publication date: January 30, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Eun-Jin Yun, Sung-Joon Kim, Sang-Hoan Chang
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Publication number: 20190189221Abstract: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines; a calculation circuit configured to perform a calculation on information bits and weight bits based on a calculation window having a first size, the information bits and weight bits being included in a user data set, the memory cell array being configured to store the user data set, the calculation circuit being further configured to receive the user data set through the page buffer circuit; and a data input/output (I/O) circuit connected to the calculation circuit, wherein the calculation circuit is further configured to provide an output data set to the data I/O circuit in response to the calculation circuit completing the calculation with respect to all of the information bits and the weight bits, and wherein the output data set corresponds to a result of the completed calculation.Type: ApplicationFiled: September 11, 2018Publication date: June 20, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Taek-Soo KIM, Chan-lk PARK, Hyun-Sung SHIN, Sang-Hoan CHANG
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Patent number: 9087220Abstract: A nonvolatile memory device includes a memory cell array configured to store an authentication key and authentication key configuration information in first and second pluralities of nonvolatile memory cells, along with data whose security is to be protected, and a control circuit controlling an operation of the memory cell array.Type: GrantFiled: April 19, 2012Date of Patent: July 21, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Hoan Chang, Kwang Jin Lee
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Patent number: 8923043Abstract: A memory device may include a normal cell which is configured to be programmed to a first resistance and stabilized as a resistance of the normal cell drifts from the first resistance to a second resistance; a flag cell which is configured to be programmed to a third resistance smaller than the first resistance and stabilized as a resistance of the flag cell drifts from the third resistance to a fourth resistance smaller than the second resistance; and a decision circuit which is configured to decide whether the flag cell has been stabilized in order to determine whether the normal cell has been stabilized.Type: GrantFiled: February 8, 2013Date of Patent: December 30, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Yang-Woo Roh, Chul Lee, Sang-Hoan Chang, Jae-Soo Lee, Joo-Young Hwang
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Patent number: 8830724Abstract: A method of operating a PRAM device includes reading a PRAM reference cell to determine an initial programmed resistance of the PRAM reference cell and determining whether the initial programmed resistance has been reduced to below a predetermined reference threshold resistance.Type: GrantFiled: June 24, 2011Date of Patent: September 9, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Sang Hoan Chang
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Publication number: 20130014269Abstract: A nonvolatile memory device includes a memory cell array configured to store an authentication key and authentication key configuration information in first and second pluralities of nonvolatile memory cells, along with data whose security is to be protected, and a control circuit controlling an operation of the memory cell array.Type: ApplicationFiled: April 19, 2012Publication date: January 10, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Hoan Chang, Kwang Jin Lee
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Phase change memory device, memory system, and programming method using variable verification pulses
Patent number: 8279664Abstract: In a method of programming a phase change memory device, write data is programmed in a plurality of phase change memory cells by applying write pulses to each of the plurality of phase change memory cells. Whether each of the phase change memory cells is programmed is verified by applying verification pulses to each of the phase-change memory cells. A number of applications for the verification pulses and the intervals between respective applications of the verification pulses are varied in accordance with a verification result for each of the phase-change memory cells.Type: GrantFiled: September 10, 2010Date of Patent: October 2, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hoan Chang, Seong-Moo Heo, Kwang-Suk Yu, Yeong-Taek Lee, Woo-Yeong Cho -
Publication number: 20120087183Abstract: A method of operating a PRAM device can be provided by reading a PRAM reference cell to determine an initial programmed resistance of the PRAM reference cell and determining whether the initial programmed resistance has been reduced to below a predetermined reference threshold resistance.Type: ApplicationFiled: June 24, 2011Publication date: April 12, 2012Inventor: Sang Hoan Chang
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Publication number: 20110063904Abstract: A method of programming a phase change memory device is disclosed. Write data is programmed in a plurality of phase change memory cells by applying write pulses to each of the plurality of phase change memory cells. Whether each of the phase change memory cells is programmed is verified by applying at least one verification pulse to each of the phase-change memory cells. A number of applications for the at least one verification pulse and the intervals between respective applications of the at least one verification pulse are varied in accordance with a verification result for each of the phase-change memory cells.Type: ApplicationFiled: September 10, 2010Publication date: March 17, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Hoan CHANG, Seong-Moo HEO, Kwang-Suk YU, Yeong-Taek LEE, Woo-Yeong CHO
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Publication number: 20110055486Abstract: A method of processing data in a resistive memory device comprises performing a write operation to store data into a resistive memory of the resistive memory device and to store program information of the data into a cache memory. The method further comprises performing a first read operation to read the program information from the cache memory during a program-to-active time, and a second read operation to read the data from the resistive memory after the program-to-active time if the program information is not read from the cache memory during the program-to-active time.Type: ApplicationFiled: August 19, 2010Publication date: March 3, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seong-Moo HEO, Sang-Hoan CHANG
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Patent number: 6821850Abstract: A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.Type: GrantFiled: July 28, 2003Date of Patent: November 23, 2004Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Sang-Hoan Chang, Ki-Seog Kim, Keun-Woo Lee, Sung-Kee Park
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Publication number: 20040071020Abstract: A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.Type: ApplicationFiled: July 28, 2003Publication date: April 15, 2004Applicant: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. a corporation of Republic of KoreaInventors: Sang-Hoan Chang, Ki-Seog Kim, Keun-Woo Lee, Sung-Kee Park
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Patent number: 6630709Abstract: A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.Type: GrantFiled: December 19, 2000Date of Patent: October 7, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Sang-Hoan Chang, Ki-Seog Kim, Keun-Woo Lee, Sung-Kee Park
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Patent number: 6391665Abstract: There is disclosed a method of monitoring a source contact in a flash memory by which whether a source contact having a narrow contact area contacts or not can be easily monitored using over-erase cell characteristic in a flash cell, in a flash memory device in which a source line is formed by a local interconnection method. In the present invention, in order to monitor a contact state at source contacts, the same voltage to the erase condition of a cell is applied to respective terminals (VG terminal, VD terminal, VS terminal and VSS terminal) wherein all the electrons existing at a floating gate in all the cells connected to the VS terminal and VSS terminal become turned on so that they can be over-erased. On the other hands, as electrons existing at the floating gate in two cells shared by any source contacts having a defect contact are not erased, the cells remain turn-off.Type: GrantFiled: November 27, 2000Date of Patent: May 21, 2002Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Sang Hoan Chang, Ki Seog Kim, Jin Shin, Keun Woo Lee
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Patent number: 6316313Abstract: There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that a well resistance and a parasitic capacitance are great and the erase speed of a device is slow in case of the conventional flash memory device, the present invention forms a well region of a sector unit by use of a metal silicide layer and defines an unit cell by use of a ploysilicon layer. Thus, it can reduce the well resistance and the parasitic capacitance. Also, it can improve the operating speed of the device and can reduce the manufacturing cost by allowing the erase operation of a cell unit.Type: GrantFiled: November 22, 2000Date of Patent: November 13, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Sung Kee Park, Ki Seog Kim, Sang Hoan Chang, Keun Woo Lee
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Patent number: 6304484Abstract: There is disclosed a multi-bit flash memory cell and programming method using the same. In order to solve the problems that the size of a cell per unit is increased, reliability of a device is degraded due to a high operating voltage and a circuit necessary for driving the cell becomes complicated, the multi-bit flash memory cell and programming method using the same according to the present invention stores information of various states, by interchangeably programs a drain and a source in a cell array of virtual ground type, in a structure in which that two types of cells look like connected serially by doping a floating gate in a flash memory cell with two regions of a N type and a P to type.Type: GrantFiled: November 27, 2000Date of Patent: October 16, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Jin Shin, Sang Hoan Chang, Seoung Ouk Choi, Keon Soo Shim
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Publication number: 20010026480Abstract: A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.Type: ApplicationFiled: December 19, 2000Publication date: October 4, 2001Inventors: Sang-Hoan Chang, Ki-Seog Kim, Keun-Woo Lee, Sung-Kee Park