Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.

Abstract: A white light emitting device includes a blue light emitting diode emitting first light having a dominant wavelength in a range of 440 nm to 460 nm, a quantum dot disposed on a path of the emitted first light and converting a first portion of the emitted first light into green light, and a fluoride phosphor disposed on the path of the emitted first light and converting a second portion of the emitted first light into red light. The quantum dot includes a core formed of a group III-V compound and a shell formed of a group II-VI compound, and the fluoride phosphor is represented by empirical formula AxMFy:Mn4+, A being at least one selected from Li, Na, K, Rb, and Cs, M being at least one selected from Si, Ti, Zr, Hf, Ge, and Sn, and the empirical formula satisfying 2?x?3 and 4?y?7.

Abstract: Disclosed is an electronic device capable of near field communication (NFC) and of achieving high integration, size reduction, and good sensitivity. The electronic device includes an antenna chip provided inside a battery protection circuit package of a battery pack and having embedded an NFC antenna therein, and an extended antenna loop electrically connected to the antenna chip and provided outside the battery protection circuit package.

Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.

Abstract: In a method of forming a wiring structure, an insulating interlayer is formed on a substrate. The insulating interlayer includes an opening and has pores distributed therein and exposed at a surface thereof. The insulating interlayer is exposed to a silane compound to form a pore sealing layer on the surface of the insulating interlayer and a sidewall of the opening. A conductive pattern filling the opening is formed on the pore sealing layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a first porous interlayer insulating film having a low dielectric constant and including a first region and a second region, a second interlayer insulating film formed on the first interlayer insulating film in the first region, a plurality of first conductive patterns formed in the second interlayer insulating film such that the plurality of first conductive patterns are spaced apart from each other, at least one second conductive pattern formed in the first interlayer insulating film in the second region and air gaps disposed at lateral sides of the plurality of first conductive patterns.

Abstract: A power MOSFET includes an insulating layer, a first conductivity type doping layer situated on a bottom of the insulating layer, a second conductivity type body situated on a bottom of the first conductivity type doping layer, a gate electrode adjacent to the bottom of the insulating layer and covered with an insulating film in other regions and projected to penetrate the second conductivity type body, and a source electrode including a first region situated on a top of the insulating layer and a second region in contact with the first conductivity type doping layer by penetrating the insulating layer.

Abstract: Methods of forming a dielectric layer are provided. The methods may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate. Each of the organic silicon precursors may include a carbon bridge and a porogen such that the preliminary dielectric layer may include carbon bridges and porogens. The methods may also include removing at least some of the porogens from the preliminary dielectric layer to form a porous dielectric layer including the carbon bridges.

Abstract: An apparatus for crystallizing an active layer of a thin film transistor, the apparatus includes a first laser irradiating a first beam toward a substrate, an amorphous layer on the substrate being crystallizable into the active layer of the thin film transistor by the first beam, and a second laser irradiating a second beam toward the substrate to heat the active layer, the second beam having an asymmetric intensity profile in a scanning direction of the first and second beams.

Abstract: A semiconductor device may include a plurality of wiring structures spaced apart from each other, a protection pattern including a metal nitride on each of the wiring structures, a spacer on a sidewall of the protection pattern, and an insulating interlayer structure containing the wiring structures and having an air gap between the wiring structures.

Abstract: A curved transparent substrate includes an alkali-free base layer having a curved shape and a compression applying layer compression applying layer which is disposed on a surface of the alkali-free base layer and applies a compression to the alkali-free base layer where an alkali ion content of the compression applying layer is greater than an alkali ion content of the alkali-free base layer.

Abstract: In a method of forming a wiring structure, an insulating interlayer is formed on a substrate. The insulating interlayer includes an opening and has pores distributed therein and exposed at a surface thereof. The insulating interlayer is exposed to a silane compound to form a pore sealing layer on the surface of the insulating interlayer and a sidewall of the opening. A conductive pattern filling the opening is formed on the pore sealing layer.

Abstract: A semiconductor device includes a plurality of wiring structures spaced apart from each other, and an insulating interlayer structure. Each of the wiring structures includes a metal pattern and a barrier pattern covering a sidewall, a bottom surface, and an edge portion of a top surface of the metal pattern and not covering a central portion of the top surface of the metal pattern. The insulating interlayer structure contains the wiring structures therein, and has an air gap between the wiring structures.

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

Abstract: A semiconductor device includes an insulating interlayer on a first region of a substrate. The insulating interlayer has a recess therein and includes a low-k material having porosity. A damage curing layer is formed on an inner surface of the recess. A barrier pattern is formed on the damage curing layer. A copper structure fills the recess and is disposed on the barrier pattern. The copper structure includes a copper pattern and a copper-manganese capping pattern covering a surface of the copper pattern. A diffusion of metal in a wiring structure of the semiconductor device may be prevented, and thus a resistance of the wiring structure may decrease.

Abstract: Disclosed is a package module of a battery protection circuit. The package module comprises: a first internal connection terminal area and a second internal connection terminal area, and in which first and second internal connection terminals connected to a battery can provided with a bare cell are respectively disposed; an external connection terminal area, in which a plurality of external connection terminals are disposed; and a protection circuit area comprising a device area in which a plurality of passive devices forming the battery protection circuit are disposed and a chip area, which is adjacent to the device area, and in which a protection IC and a dual FET chip forming the battery protection circuit are disposed, are disposed between the external connection terminal area and the second internal connection terminal area.

Abstract: Provided is an antenna module package including a substrate, a wireless card payment antenna structure mounted on the substrate and including a first antenna chip and wireless card payment matching elements electrically connected to the first antenna chip, a near field communication (NFC) antenna structure mounted on the substrate, sharing the first antenna chip, and including an extended NFC antenna loop and NFC matching elements electrically connected to the first antenna chip, and a wireless charging antenna structure mounted on the substrate and including a second antenna chip, and an extended wireless charging antenna loop and wireless charging matching elements electrically connected to the second antenna chip.

Abstract: A semiconductor device is provided. The semiconductor device includes a first porous interlayer insulating film having a low dielectric constant and including a first region and a second region, a second interlayer insulating film formed on the first interlayer insulating film in the first region, a plurality of first conductive patterns formed in the second interlayer insulating film such that the plurality of first conductive patterns are spaced apart from each other, at least one second conductive pattern formed in the first interlayer insulating film in the second region and air gaps disposed at lateral sides of the plurality of first conductive patterns.

Abstract: Disclosed is a substrate for a curved display device, including: an alkali-free glass substrate that does not contain an alkali metal oxide; and an inorganic coating part formed on at least one of a display surface and a lateral surface of the alkali-free glass substrate, and having a larger value of a coefficient of thermal expansion than that of the glass substrate.

Abstract: Methods of forming a wiring structure are provided including forming an insulating interlayer on a substrate and forming a sacrificial layer on the insulating interlayer. The sacrificial layer is partially removed to define a plurality of openings. Wiring patterns are formed in the openings. The sacrificial layer is transformed into a modified sacrificial layer by a plasma treatment. The modified sacrificial layer is removed by a wet etching process. An insulation layer covering the wiring patterns is formed on the insulating interlayer. The insulation layer defines an air gap therein between neighboring wiring patterns.