Abstract: A system for manufacturing a lithium ion secondary battery includes an unwinder supplying a current collector to be coated to a predetermined position, a coating device coating a coating liquid on the current collector, a drying device drying the coated current collector, and a rewinder winding the coated current collector passing through the drying device at a predetermined position.

Abstract: A positive electrode active material in a form of a single particle includes a lithium transition metal oxide in a form of a single particle, a coating portion containing cobalt which is formed on the lithium transition metal oxide in the form of a single particle, and LiCoO2 in a form of an island which is discontinuously formed on a surface. A ratio of an intensity of a peak ranging from 550 cm?1 to 620 cm?1 corresponding to an A1g vibration mode of LiCoO2 to an intensity of a peak ranging from 500 cm?1 to 600 cm?1 corresponding to an A1g vibration mode of LiNiO2 in a Raman spectrum of the surface is in a range of 0.1 to 1. Also provided is a method of preparing a positive electrode active material in a form of a single particle.

Abstract: A memory apparatus is configured to generate refresh addresses with different values in response to one refresh command and an address, and perform a plurality of refresh operations with time differences in response to the refresh addresses. Herein, the refresh operations are performed within a refresh row cycle time.

Abstract: A memory apparatus is configured to generate refresh addresses with different values in response to one refresh command and an address, and perform a plurality of refresh operations with time differences in response to the refresh addresses. Herein, the refresh operations are performed within a refresh row cycle time.

Abstract: A circuit for controlling the loading of write data in a semiconductor memory device includes a global bus; a data block configured to selectively load data of a predetermined first burst length or data of a second burst length, which is a half of the first burst length, for writing on the global bus in response to a control signal; and a memory bank configured to write the data of the first burst length or the data of the second burst length.

Abstract: A circuit for controlling the loading of write data in a semiconductor memory device includes a global bus; a data block configured to selectively load data of a predetermined first burst length or data of a second burst length, which is a half of the first burst length, for writing on the global bus in response to a control signal; and a memory bank configured to write the data of the first burst length or the data of the second burst length.