Patents by Inventor Sang-Hun Seo
Sang-Hun Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200161096Abstract: Provided are a plasma generating apparatus and a substrate treating apparatus. The plasma generating apparatus includes a plurality of ground electrodes arranged inside a vacuum container and extending parallel to each other and power electrodes arranged between the ground electrodes. An area where a distance between the ground electrode and the power electrode is constant exists, and the power electrodes are tapered in a direction facing the substrate. The power electrodes are connected to an RF power source, and height of the power electrode is greater than that of the ground electrode in the direction facing the substrate.Type: ApplicationFiled: November 19, 2019Publication date: May 21, 2020Applicants: Jusung Engineering Co., Ltd., Korea Advanced Institute of Science and TechnologyInventors: Hong-Young CHANG, Sang-Hun Seo, Yun-Seong Lee
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Patent number: 10553406Abstract: Provided are a plasma generating apparatus and a substrate treating apparatus. The plasma generating apparatus includes a plurality of ground electrodes arranged inside a vacuum container and extending parallel to each other and power electrodes arranged between the ground electrodes. An area where a distance between the ground electrode and the power electrode is constant exists, and the power electrodes are tapered in a direction facing the substrate. The power electrodes are connected to an RF power source, and height of the power electrode is greater than that of the ground electrode in the direction facing the substrate.Type: GrantFiled: March 29, 2012Date of Patent: February 4, 2020Assignees: Jusung Engineering Co., LTD., Korea Advanced Institute of Science and TechnologyInventors: Hong-Young Chang, Sang-Hun Seo, Yun-Seong Lee
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Publication number: 20190006156Abstract: A plasma processing apparatus includes an electrostatic chuck configured to adsorb and hold a wafer, a focus ring disposed to surround an upper edge of the electrostatic chuck, an insulating tube disposed to cover a side surface of the electrostatic chuck, and a conductive tube disposed to cover the insulating tube.Type: ApplicationFiled: January 4, 2017Publication date: January 3, 2019Inventors: Sang-Hun SEO, Sanghyun CHUNG
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Publication number: 20140320016Abstract: A plasma generating apparatus and a substrate processing apparatus are disclosed. The plasma generating apparatus includes a disk-shaped first electrode receiving first RF power of a first frequency to generate plasma, a washer-type second electrode disposed around the circumference of the first electrode and receiving second RF power of a second frequency, an insulating spacer disposed between the first electrode and the second electrode, a first RF power source supplying power to the first electrode, and a second RF power source supplying power to the second electrode.Type: ApplicationFiled: July 11, 2014Publication date: October 30, 2014Inventors: Hong-Young CHANG, Sang-Hun SEO, Gi-Jung PARK
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Publication number: 20140007812Abstract: Provided are a plasma generating apparatus and a substrate treating apparatus. The plasma generating apparatus includes a plurality of ground electrodes arranged inside a vacuum container and extending parallel to each other and power electrodes arranged between the ground electrodes. An area where a distance between the ground electrode and the power electrode is constant exists, and the power electrodes are tapered in a direction facing the substrate. The power electrodes are connected to an RF power source, and height of the power electrode is greater than that of the ground electrode in the direction facing the substrate.Type: ApplicationFiled: March 29, 2012Publication date: January 9, 2014Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, JUSUNG ENGINEERING CO., LTD.Inventors: Hong-Young Chang, Sang-Hun Seo, Yun-Seong Lee
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Publication number: 20130255575Abstract: Provided is a plasma generator which includes a vacuum chamber, a plurality of ground electrodes disposed inside the vacuum container and extending in parallel to each other, a plurality of power electrodes disposed between the ground electrodes inside the vacuum container, and a plurality of electrodes dielectrics disposed between the power electrodes and the ground electrodes inside the vacuum container. The power electrodes are connected to an RF power source.Type: ApplicationFiled: May 30, 2013Publication date: October 3, 2013Inventors: Hong-Young CHANG, Sang-Hun SEO, Jung Hwan IN, Hun-Su LEE, Yun-Seong LEE
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Patent number: 7491344Abstract: Disclosed herein is a method for etching a face of an object and more particularly a method for etching a rear face of a silicon substrate. The object having a silicon face is positioned so as to be spaced apart from a plasma-generating member by a predetermined interval distance. The plasma-generating member generates arc plasmas to form a plasma region. A reaction gas is allowed to pass through the plasma region to generate radicals having high energies and high densities. The radicals react with the object to etch the face of the object. The face of the object can be rapidly and uniformly etched.Type: GrantFiled: November 4, 2003Date of Patent: February 17, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Heung-Sik Park, Chang-Jin Kang, Tae-Hyuk Ahn, Kyeong-Koo Chi, Sang-Hun Seo
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Patent number: 7258811Abstract: A wafer stage including an electrostatic chuck and a method for dechucking a wafer using the wafer stage are provided, wherein, the wafer stage includes an electrostatic chuck support, an electrostatic chuck, a lifting means, and a grounding means including a device for connecting the interconnections for grounding the lifting means. According to the method for dechucking a wafer, when a lifting means is in contact with a rear side of the wafer, the lifting means is grounded. Then, an electrostatic chuck is neutralized by supplying power to electrostatic electrodes, and the wafer is neutralized by supplying plasma to the wafer.Type: GrantFiled: June 10, 2004Date of Patent: August 21, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-woong Chu, Kyeong-koo Chi, Ji-soo Kim, Seung-pil Chung, Sang-hun Seo
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Publication number: 20050151173Abstract: A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.Type: ApplicationFiled: December 28, 2004Publication date: July 14, 2005Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-Hun Seo, Seung-Hyun Park, Han-Sin Lee, Moo-Sung Kim, Won-Suk Yang
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Patent number: 6855590Abstract: A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.Type: GrantFiled: August 28, 2003Date of Patent: February 15, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hun Seo, Seung-Hyun Park, Han-Sin Lee, Moo-Sung Kim, Won-Suk Yang
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Publication number: 20040223286Abstract: A wafer stage including an electrostatic chuck and a method for dechucking a wafer using the wafer stage are provided, wherein, the wafer stage includes an electrostatic chuck support, an electrostatic chuck, a lifting means, and a grounding means including a device for connecting the interconnections for grounding the lifting means. According to the method for dechucking a wafer, when a lifting means is in contact with a rear side of the wafer, the lifting means is grounded. Then, an electrostatic chuck is neutralized by supplying power to electrostatic electrodes, and the wafer is neutralized by supplying plasma to the wafer.Type: ApplicationFiled: June 10, 2004Publication date: November 11, 2004Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-woong Chu, Kyeong-koo Chi, Ji-soo Kim, Seung-pil Chung, Sang-hun Seo
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Patent number: 6793767Abstract: A wafer stage including an electrostatic chuck and a method for dechucking a wafer using the wafer stage are provided, wherein, the wafer stage includes an electrostatic chuck support, an electrostatic chuck, a lifting means, and a grounding means including a device for connecting the interconnections for grounding the lifting means. According to the method for dechucking a wafer, when a lifting means is in contact with a rear side of the wafer, the lifting means is grounded. Then, an electrostatic chuck is neutralized by supplying power to electrostatic electrodes, and the wafer is neutralized by supplying plasma to the wafer.Type: GrantFiled: September 14, 2001Date of Patent: September 21, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-woong Chu, Kyeong-koo Chi, Ji-soo Kim, Seung-pil Chung, Sang-hun Seo
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Publication number: 20040144981Abstract: A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.Type: ApplicationFiled: August 28, 2003Publication date: July 29, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-Hun Seo, Seung-Hyun Park, Han-Sin Lee, Moo-Sung Kim, Won-Suk Yang
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Patent number: 6767834Abstract: A method of manufacturing a contact of a semiconductor device includes a series of pretreatment processes each performed in a plasma pretreatment module. A semiconductor substrate has an interlayer formed on an underlayer of a material containing silicon. A contact hole is formed in the interlayer to expose a surface of the underlayer. Subsequently, the semiconductor substrate is loaded into a plasma pretreatment module. The photoresist pattern is removed by ashing in the plasma pretreatment module. A damaged layer at the surface exposed by the contact hole is then removed in the plasma pretreatment module. Subsequently, the semiconductor substrate is pre-cleaned in the plasma pretreatment module. The semiconductor substrate is then transferred, while in a vacuum, to a deposition module. There, an upper layer is formed on the substrate to fill the contact hole.Type: GrantFiled: October 25, 2001Date of Patent: July 27, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-pil Chung, Kyeong-koo Chi, Ji-soo Kim, Chang-woong Chu, Sang-hun Seo
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Publication number: 20040089632Abstract: Disclosed herein is a method for etching a face of an object and more particularly a method for etching a rear face of a silicon substrate. The object having a silicon face is positioned so as to be spaced apart from a plasma-generating member by a predetermined interval distance. The plasma-generating member generates arc plasmas to form a plasma region. A reaction gas is allowed to pass through the plasma region to generate radicals having high energies and high densities. The radicals react with the object to etch the face of the object. The face of the object can be rapidly and uniformly etched.Type: ApplicationFiled: November 4, 2003Publication date: May 13, 2004Inventors: Heung-Sik Park, Chang-Jin Kang, Tae-Hyuk Ahn, Kyeong-Koo Chi, Sang-Hun Seo
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Patent number: 6534921Abstract: A method of removing metal-containing polymeric material and ion implanted or plasma damaged photoresist from a surface using a plasma jet system, by generating radicals having high energy and high density from atmospheric plasma by introducing a reactant gas to the plasma, and placing the surface at a distance from the plasma, whereby ionic reaction on the surface is minimized while the removing action of the radicals on the surface is maintained.Type: GrantFiled: November 9, 2000Date of Patent: March 18, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hun Seo, Kyeong-Koo Chi, Ji-Soo Kim, Chang-Woong Chu, Seung-Pil Chung
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Patent number: 6465346Abstract: A conducting line of a semiconductor device using an aluminum oxide layer as a hard mask, and a method of forming the conducting line. The conducting line, such as a gate line or a bit line of a semiconductor device, includes a conductive layer formed on a semiconductor substrate, a capping insulation layer formed on the conductive layer, and an aluminum oxide layer formed on the capping insulation layer, with the aluminum oxide layer being used as a hard mask.Type: GrantFiled: February 28, 2001Date of Patent: October 15, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-soo Kim, Wan-jae Park, Chang-woong Chu, Sang-hun Seo
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Publication number: 20020113310Abstract: A conducting line of a semiconductor device using an aluminum oxide layer as a hard mask, and a method of forming the conducting line. The conducting line, such as a gate line or a bit line of a semiconductor device, includes a conductive layer formed on a semiconductor substrate, a capping insulation layer formed on the conductive layer, and an aluminum oxide layer formed on the capping insulation layer, with the aluminum oxide layer being used as a hard mask.Type: ApplicationFiled: February 28, 2001Publication date: August 22, 2002Inventors: Ji-Soo Kim, Wan-Jae Park, Chang-Woong Chu, Sang-Hun Seo
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Publication number: 20020078891Abstract: A wafer stage including an electrostatic chuck and a method for dechucking a wafer using the wafer stage are provided, wherein, the wafer stage includes an electrostatic chuck support, an electrostatic chuck, a lifting means, and a grounding means including a device for connecting the interconnections for grounding the lifting means. According to the method for dechucking a wafer, when a lifting means is in contact with a rear side of the wafer, the lifting means is grounded. Then, an electrostatic chuck is neutralized by supplying power to electrostatic electrode, and the wafer is neutralized by supplying plasma to the wafer.Type: ApplicationFiled: September 14, 2001Publication date: June 27, 2002Inventors: Chang-Woong Chu, Kyeong-Koo Chi, Ji-Soo Kim, Seung-Pil Chung, Sang-Hun Seo
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Publication number: 20020064944Abstract: A method of manufacturing a contact of a semiconductor device includes a series of pretreatment processes each performed in a plasma pretreatment module. A semiconductor substrate has an interlayer formed on an underlayer of a material containing silicon. A contact hole is formed in the interlayer to expose a surface of the underlayer. Subsequently, the semiconductor substrate is loaded into a plasma pretreatment module. The photoresist pattern is removed by ashing in the plasma pretreatment module. A damaged layer at the surface exposed by the contact hole is then removed in the plasma pretreatment module. Subsequently, the semiconductor substrate is pre-cleaned in the plasma pretreatment module. The semiconductor substrate is then transferred, while in a vacuum, to a deposition module. There, an upper layer is formed on the substrate to fill the contact hole. SEC.Type: ApplicationFiled: October 25, 2001Publication date: May 30, 2002Inventors: Seung-pil Chung, Kyeong-koo Chi, Ji-soo Kim, Chang-woong Chu, Sang-hun Seo