Abstract: A multilayer electronic component includes a body including a dielectric layer and first and second internal electrodes alternately disposed with the dielectric layer therebetween, and including first and second surfaces opposing each other in a first direction, third and fourth surfaces opposing each other in a second direction, and fifth and sixth surfaces opposing each other in a third direction; and an external electrode including a connection portion disposed on the third or fourth surface and a band portion extending from the connection portion to portions of the first and second surfaces, wherein the external electrode includes a sputtered layer disposed in the connection portion and contacting the first or second internal electrode and including Cu, an oxide layer disposed on the sputtered layer and including a Cu oxide, and a conductive polymer layer disposed in the band portion and including a polymer material.

Abstract: A photomask includes a mask substrate. A reflective layer is disposed on a first surface of the mask substrate. A capping layer is disposed on the reflective layer. An absorber layer pattern is disposed on the capping layer. The absorber layer pattern defines an opening that light sources of extreme ultraviolet wavelengths pass through. A side wall of the absorber layer pattern exposed by the opening includes an inclined surface on an upper portion disposed away from the capping layer and a curved surface on a lower portion adjacent to the capping layer.

Abstract: In one example, an electronic device comprises a substrate defining an opening between interior sidewalls. An electronic component is disposed in the opening. A lid is disposed beneath the substrate and a first side of the electronic component, and the lid is thermally coupled to the electronic component. Component interconnects can be coupled to a second side of the electronic component opposite the first side. An antenna structure is disposed over the electronic component and electronically coupled to electronic component through the component interconnects. Other examples and related methods are also disclosed herein.

Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

Abstract: A catalyst ink for plating and a method for electrochemically manufacturing an electronic device by using same are disclosed. The present invention provides a catalyst ink for plating, comprising: a polymer binder; a metal ion as a catalyst; a silane coupling agent for coupling the metal ion and the polymer; and a solvent, wherein the polymer has a lower critical solution temperature in the temperature-composition phase diagram for a solvent-polymer binary system, and the lower critical solution temperature is 30° C. or higher. According to the present invention, a high resolution plated pattern having a line width and a width between lines can be manufactured.

Abstract: Provided are a method and apparatus for correcting a colored image. The method of correcting a colored image includes obtaining a colored image by inputting a sketch image to a first artificial neural network, receiving user input data for a target area in the colored image, and obtaining a corrected image in which a color state of the target area has been changed, by inputting the sketch image and the user input data to a second artificial neural network.

Abstract: In one example, an electronic device includes a substrate and a cover structure. The cover structure includes an upper cover wall comprising an upper wall outer surface and an upper wall inner surface opposite to the upper wall outer surface, cover sidewalls extending from the upper wall inner surface and coupled to the substrate. The upper cover wall and the cover sidewalls define a cavity. A channel structure is in the upper cover wall extending inward from the upper wall inner surface. A first electronic component is coupled to the substrate within the cavity and a thermal interface material (TIM) is coupled to the upper wall inner surface and the first electronic component. A portion of the TIM is within the channel structure. Other examples and related methods are also disclosed herein.

Abstract: In one example, an electronic device includes a first substrate and a second substrate. The first substrate includes a substrate first side, a substrate second side, and a first conductive structure. An inner electronic component is coupled to the first conductive structure proximate to the substrate second side. An outer electronic component is coupled to the first conductive structure proximate to the substrate first side. The outer electronic component includes a body and a groove in the body configured to couple with an external interconnect. Inner interconnects couple the first substrate to the second substrate. The first substrate, the second substrate, the inner electronic component, and the outer electronic component are in a stacked configuration. The inner electronic component is interposed between the first substrate and the second substrate. Other examples and related methods are also disclosed herein.

Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

Abstract: A semiconductor device includes an active pattern with a lower pattern and sheet patterns spaced apart from the lower pattern, a gate structure on the lower pattern and having a gate electrode and a gate insulating film that surround each of the sheet patterns, a gate capping pattern on the gate structure, a gate etching stop pattern between the gate capping pattern and the gate structure, a gate spacer along a sidewall of the gate capping pattern, a source/drain pattern on the gate structure, a gate contact through the gate capping pattern and connected to the gate electrode, upper surfaces of the gate contact and gate spacer being coplanar, and a source/drain contact on the source/drain pattern and connected to the source/drain pattern.

Abstract: The present invention relates to silver ink for printing a three dimensional microstructure and a 3D printing method using the same. The present invention provides a method for printing a 3-dimensional silver structure pattern, the method including: a step of providing a nozzle with liquid ink including capped silver nanoparticles and exhibiting Newtonian fluid behavior; a step of forming, at a predetermined point on a substrate, a meniscus of the liquid ink with ink extruded from the nozzle; a step of allowing the ink of the nozzle to be extruded by means of the surface tension of the meniscus while moving the nozzle along a path in a direction perpendicular to the substrate, in a direction parallel to the substrate, or according to a combination of said directions; and a step of forming a silver structure pattern corresponding to the movement path of the nozzle by evaporating a solvent from the extruded ink from the region closer to the substrate.

Abstract: A semiconductor device including a substrate; first and second active patterns on the substrate, extending in a first direction and spaced apart in a second direction; gate electrodes on the first and second active patterns and extending in the second direction; a first gate separation structure between the first and second active patterns, extending in the first direction, and separating the gate electrodes; and a first element separation structure between the gate electrodes, extending in the second direction, and separating the second active pattern, wherein a distance to a first side of a first portion of the first gate separation structure is smaller than a distance to the first side of a second portion of the first gate separation structure, and a distance to the second side of the first portion is smaller than a distance from the second active pattern to the second side of the second portion.

Abstract: An on-chip temperature sensor for generating a digital output signal representing a temperature value includes: a proportional to absolute temperature (PTAT) buffer for alternately generating a first voltage signal representing a first temperature of the PTAT buffer and a second voltage signal representing a second temperature of the PTAT buffer; an analog to digital (A/D) converter, coupled to the PTAT buffer, for converting the first voltage signal to a first digital voltage signal and for converting the second voltage signal to a second digital voltage signal; and a digital output generating block, for receiving the first digital voltage signal and the second digital voltage signal, and comparing a difference between the first digital voltage signal and the second digital voltage signal with a digital voltage reference signal to generate the digital output signal.

Abstract: An on-chip temperature sensor for generating a digital output signal representing a temperature value includes: a proportional to absolute temperature (PTAT) buffer for alternately generating a first voltage signal representing a first temperature of the PTAT buffer and a second voltage signal representing a second temperature of the PTAT buffer; an analog to digital (A/D) converter, coupled to the PTAT buffer, for converting the first voltage signal to a first digital voltage signal and for converting the second voltage signal to a second digital voltage signal; and a digital output generating block, for receiving the first digital voltage signal and the second digital voltage signal, and comparing a difference between the first digital voltage signal and the second digital voltage signal with a digital voltage reference signal to generate the digital output signal.

Abstract: A catalyst ink for plating and a method for electrochemically manufacturing an electronic device by using same are disclosed. The present invention provides a catalyst ink for plating, comprising: a polymer binder; a metal ion as a catalyst; a silane coupling agent for coupling the metal ion and the polymer; and a solvent, wherein the polymer has a lower critical solution temperature in the temperature-composition phase diagram for a solvent-polymer binary system, and the lower critical solution temperature is 30° C. or higher. According to the present invention, a high resolution plated pattern having a line width and a width between lines can be manufactured.

Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

Abstract: The present invention relates to silver ink for printing a three dimensional microstructure and a 3D printing method using the same. The present invention provides a method for printing a 3-dimensional silver structure pattern, the method including: a step of providing a nozzle with liquid ink including capped silver nanoparticles and exhibiting Newtonian fluid behavior; a step of forming, at a predetermined point on a substrate, a meniscus of the liquid ink with ink extruded from the nozzle; a step of allowing the ink of the nozzle to be extruded by means of the surface tension of the meniscus while moving the nozzle along a path in a direction perpendicular to the substrate, in a direction parallel to the substrate, or according to a combination of said directions; and a step of forming a silver structure pattern corresponding to the movement path of the nozzle by evaporating a solvent from the extruded ink from the region closer to the substrate.

Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.