Abstract: A semiconductor memory device and a method for fabricating the same are provided. The semiconductor memory device includes a plurality of gate stacks separated by a plurality of slit structures, and each of the gate stacks includes: a first stack including three or more first conductive patterns spaced apart from one another at substantially a same level; a second stack formed on the first stack and including second conductive patterns and interlayer dielectric layers alternately stacked; and a plurality of channel structures penetrating the second stack and the first stack.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a source structure, a first drain select line spaced apart from the source structure, first to fourth bit lines of a first group of bit lines spaced apart from the first drain select line, first to fourth channel structures of a first column of channel structures extending from the source structure to pass through the first drain select line, and first to fourth contact plugs of the first contact group of contact plugs connecting the first to fourth channel structures of the first column of channel structures to the first to fourth bit lines of the first group of bit lines, respectively, and in which each of the first to fourth channel structures of the first column of channel structures extend to overlap the first to fourth bit lines of the first group of bit lines.

Abstract: A method of manufacturing a semiconductor memory device includes: forming a stack structure including interlayer insulating layers and sacrificial layers, which are alternately stacked; forming an upper insulating layer covering the stack structure; forming a preliminary isolation structure in the upper insulating layer; forming a slit penetrating the upper insulating layer and the stack structure; replacing the sacrificial layers with conductive patterns through the slit; and opening a preliminary trench structure defined in the upper insulating layer by removing the preliminary isolation structure.

Abstract: The present disclosure technology provides memory cells and a semiconductor device including the same. According to the present technology, a semiconductor device comprises a plurality of active layers vertically stacked along a first direction over a substrate and horizontally extending along a second direction crossing the first direction; a plurality of bit lines coupled to respective first sides of the active layers and horizontally extending in a third direction crossing the first direction and the second direction; a plurality of capacitors coupled to respective second sides of the active layers; a word line vertically extending through the active layers along the first direction; an upper-level interconnection coupled to an upper end of the word line; and a lower-level interconnection coupled to a lower end of the word line.

Abstract: A semiconductor memory device and a method for fabricating the same are provided. The semiconductor memory device includes a plurality of gate stacks separated by a plurality of slit structures, and each of the gate stacks includes: a first stack including three or more first conductive patterns spaced apart from one another at substantially a same level; a second stack formed on the first stack and including second conductive patterns and interlayer dielectric layers alternately stacked; and a plurality of channel structures penetrating the second stack and the first stack.

Abstract: The present disclosure technology provides memory cells and a semiconductor device including the same. According to the present technology, a semiconductor device comprises a plurality of active layers vertically stacked along a first direction over a substrate and horizontally extending along a second direction crossing the first direction; a plurality of bit lines coupled to respective first sides of the active layers and horizontally extending in a third direction crossing the first direction and the second direction; a plurality of capacitors coupled to respective second sides of the active layers; a word line vertically extending through the active layers along the first direction; an upper-level interconnection coupled to an upper end of the word line; and a lower-level interconnection coupled to a lower end of the word line.

Abstract: A manufacturing method of a semiconductor device includes: forming pillars in a first region of a stack structure in which interlayer insulating layers and sacrificial insulating layers are alternately stacked; forming a slit in a second region of the stack structure; and removing the sacrificial insulating layers in the first region. In the removing of the sacrificial insulating layers in the first region, a portion of each of the sacrificial insulating layers, which is adjacent to the slit, and a portion of each of the sacrificial insulating layers, which is disposed between the pillars, may be removed using different etching materials.

Abstract: A manufacturing method of a semiconductor device includes: forming pillars in a first region of a stack structure in which interlayer insulating layers and sacrificial insulating layers are alternately stacked; forming a slit in a second region of the stack structure; and removing the sacrificial insulating layers in the first region. In the removing of the sacrificial insulating layers in the first region, a portion of each of the sacrificial insulating layers, which is adjacent to the slit, and a portion of each of the sacrificial insulating layers, which is disposed between the pillars, may be removed using different etching materials.

Abstract: A semiconductor device may include pipe channel layer, and a pipe gate surrounding the pipe channel layer. The semiconductor device may include an oxidization layer formed between the pipe gate and the pipe channel layer. The semiconductor device may include a source side channel layer and a drain side channel layer extended from the pipe channel layer to protrude further than the oxidization layer.

Abstract: Provided herein is a semiconductor device. The semiconductor device includes: a lower conductive pattern; a lower memory string conductive pattern disposed over the lower conductive pattern; a stack of upper memory string conductive patterns, wherein the stack is disposed over the lower memory string conductive pattern; a lower pad pattern extending from the lower memory string conductive pattern; upper pad patterns respectively extending from the upper memory string conductive patterns; a floating conductive pattern disposed under below the lower pad pattern, the floating conductive pattern overlapping the lower pad pattern; and a contact plug coming into contact with the lower pad pattern and overlapping the floating conductive pattern.

Abstract: Provided herein is a semiconductor device. The semiconductor device includes: a lower conductive pattern; a lower memory string conductive pattern disposed over the lower conductive pattern; a stack of upper memory string conductive patterns, wherein the stack is disposed over the lower memory string conductive pattern; a lower pad pattern extending from the lower memory string conductive pattern; upper pad patterns respectively extending from the upper memory string conductive patterns; a floating conductive pattern disposed under below the lower pad pattern, the floating conductive pattern overlapping the lower pad pattern; and a contact plug coming into contact with the lower pad pattern and overlapping the floating conductive pattern.

Abstract: A semiconductor device may include pipe channel layer, and a pipe gate surrounding the pipe channel layer. The semiconductor device may include an oxidization layer formed between the pipe gate and the pipe channel layer. The semiconductor device may include a source side channel layer and a drain side channel layer extended from the pipe channel layer to protrude further than the oxidization layer.

Abstract: A semiconductor device may include pipe channel layer, and a pipe gate surrounding the pipe channel layer. The semiconductor device may include an oxidization layer formed between the pipe gate and the pipe channel layer. The semiconductor device may include a source side channel layer and a drain side channel layer extended from the pipe channel layer to protrude further than the oxidization layer.

Abstract: The present technology includes a semiconductor memory device, including a channel layer and interlayer insulation layers surrounding the channel layer. The interlayer insulation layers are stacked with a trench interposed therebetween. A seed pattern is formed on a surface of the trench and a metal layer is formed on the seed pattern in the trench.

Abstract: A semiconductor device may include pipe channel layer, and a pipe gate surrounding the pipe channel layer. The semiconductor device may include an oxidization layer formed between the pipe gate and the pipe channel layer. The semiconductor device may include a source side channel layer and a drain side channel layer extended from the pipe channel layer to protrude further than the oxidization layer.

Abstract: The present technology includes a semiconductor memory device, including a channel layer and interlayer insulation layers surrounding the channel layer. The interlayer insulation layers are stacked with a trench interposed therebetween. A seed pattern is formed on a surface of the trench and a metal layer is formed on the seed pattern in the trench.

Abstract: The present technology includes a semiconductor memory device, including a channel layer and interlayer insulation layers surrounding the channel layer. The interlayer insulation layers are stacked with a trench interposed therebetween. A seed pattern is formed on a surface of the trench and a metal layer is formed on the seed pattern in the trench.

Abstract: A method for fabricating a semiconductor device is provided. A substrate includes two different regions, each of which has a different pattern density. A polish target layer is formed over the substrate to cover the patterns in the regions and a planarization guide layer is formed along a top surface of the polish target layer. The planarization guide layer has a polish selectivity ratio with respect to the polish target layer. Subsequently, the planarization guide layer formed in a first region is removed such that the planarization guide layer remains only in a second region having the patterns with low pattern density and the remaining planarization guide layer and the polish target layer are polished to remove a step between the first and second regions.

Abstract: A method for forming a nonvolatile memory device includes forming a tunnel insulation layer and a first conductive layer over a substrate. A trench is formed by partially etching the first conductive layer, the tunnel insulation layer and the substrate, thereby forming a resultant structure. An insulation layer is formed over the resultant structure to fill the trench. The insulation layer polished using a slurry including a polisher diluted with deionized water to expose the first conductive layer.

Abstract: A method for forming an isolation structure of a semiconductor device including a substrate where a gate insulating layer, a gate conductive layer, and a pad nitride layer are already formed includes etching the pad nitride layer, the gate conductive layer, the gate insulating layer and a portion of the substrate to form a trench, forming a wall oxide layer along an inner surface of the trench, forming a first insulating layer over a first resulting structure, including the wall oxide layer, to partially fill the trench, forming a second insulating layer using a spin coating method over a second resulting structure, including the first insulating layer, to fill the trench, polishing the first and second insulating layers using the pad nitride layer as a polish stop layer, removing the pad nitride layer, recessing the first and second insulating layers, and recessing the second insulating layer to a predetermined depth.