Abstract: A memory may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a row control circuit. The second wafer may include a second logic structure including a column control circuit.

Abstract: The present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, 3D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.

Abstract: A camera module includes a lens barrel; an actuator driving the lens barrel in a direction perpendicular to an optical axis; and an aperture module adjusting an amount of light incident in the lens barrel. The aperture module includes an aperture coupled to the lens barrel, a magnet provided on one side of the aperture, a coil disposed opposite to the magnet, a position detector detecting a position of the magnet to generate a feedback signal, and a driver comparing an input signal indicating a target position of the magnet with the feedback signal to calculate an error value and generating a driving signal according to the calculated error value. The driver compares a current position of the lens barrel with a neutral position of the lens barrel to generate a compensation signal and compensates for one of the input signal and the feedback signal based on the compensation signal.

Abstract: A camera module includes a lens barrel; an actuator driving the lens barrel in a direction perpendicular to an optical axis; and an aperture module adjusting an amount of light incident in the lens barrel. The aperture module includes an aperture coupled to the lens barrel, a magnet provided on one side of the aperture, a coil disposed opposite to the magnet, a position detector detecting a position of the magnet to generate a feedback signal, and a driver comparing an input signal indicating a target position of the magnet with the feedback signal to calculate an error value and generating a driving signal according to the calculated error value. The driver compares a current position of the lens barrel with a neutral position of the lens barrel to generate a compensation signal and compensates for one of the input signal and the feedback signal based on the compensation signal.

Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.

Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.

Abstract: The present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, 3D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.

Abstract: A method for forming a high aspect ratio feature is disclosed. The method includes depositing one or more silicon oxide/silicon nitride containing stacks on a substrate by depositing a first film layer on the substrate from a first plasma and depositing a second film layer having a refractive index on the first film layer from a second plasma. A predetermined number of first film layers and second film layers are deposited on the substrate. The first film layer and the second film layer are either a silicon oxide layer or a silicon nitride layer and the first film layer is different from the second film layer. The method further includes depositing a third film layer from a third plasma and depositing a fourth film layer on the third film layer from a fourth plasma. The fourth film layer has a refractive index greater than the first refractive index.

Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.

Abstract: Provided is a secondary battery pack including a plurality of secondary battery modules including a plurality of secondary battery cells stacked in parallel to each other in a vertical direction, a cover, and a switch installed at an upper side of the one end in the horizontal direction of the cover, a housing, a Power Relay Assembly (PRA) including a relay electrically connected to the secondary battery cells and switches, for transmitting charging power supplied from the outside to the secondary battery cells when the relay is in a close state and changing the relay to an open state when the switch is pushed according to pressure applied to an upper side from a lower surface of the cover, and a Battery Management System (BMS) for controlling the Power Relay Assembly (PRA).

Abstract: An exemplary embodiment provides a conductive connecting member, and a display device including the same, that includes a flexible elongated body and terminals formed at opposite ends of the body to be electrically connected to the body, wherein the body may include terminal areas in which the terminals are formed and a central area disposed between the terminal areas, and wherein two or more recess portions may be formed in edges of the body within the central area of the body.

Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.

Abstract: A lens may include: a lens part including an incidence surface onto which light is incident and a emission surface through which the light incident onto the incidence surface is emitted, and an outer surface which reflects the light incident onto the incidence surface toward the emission surface; and a holder part including a lens housing integrally connected with edge of the emission surface and surrounds an outer peripheral of the lens part, and at least one alignment protrusion located at a lower portion of the lens housing.

Abstract: An optical semiconductor lighting apparatus according to exemplary embodiments of the present invention provides a heat radiation member having a heat radiation plate where heat radiation fins are disposed radially, a cooling member disposed in an internal space at the center part of the heat radiation plate which inner curved portions of the heat radiation fins form, a light emitting member coupled to a lower surface of the heat radiation plate, and a cover coupled to the outer edge of the heat radiation member while covering the cooling member wherein the heat radiation fins comprise a first heat radiation fin and a second heat radiation fin which is lower than the first heat radiation fin.

Abstract: A light emitting diode (LED) lighting apparatus may include: a power supply unit configured to provide a constant DC current; a light emitting module comprising a printed circuit board (PCB) and a plurality of LEDs disposed on a first side of the PCB, wherein the lighting emitting module is configured to receive the constant direct current (DC) current; and a fan module configured to receive a constant DC voltage from the light emitting module, wherein the constant DC voltage is a sum of the forward voltages of at least two LEDs of the plurality of LEDs.

Abstract: An optical semiconductor lighting apparatus including an upper part including a cover and a cooling member coupled to a lower surface of the cover and a lower part including a housing forming an inner space, a heat radiation member coupled to a lower side of the housing, and a light emitting member coupled to a lower surface of the heat radiation member. The upper part is mounted on top of the lower part and the cooling member is disposed over the heat radiation member at a predetermined distance.

Abstract: A light emitting diode (LED) lighting apparatus includes: a power supply unit configured to convert AC current and/or voltage into DC current and/or voltage and output the converted DC current and/or voltage, a light emitting module comprising a printed circuit board (PCB) and a plurality of LEDs disposed on a first side of the PCB, wherein the light emitting module is configured to receive the DC current from the power supply unit, a fan module configured to receive the DC voltage from the power supply unit, and a temperature sensor configured to generate temperature information and transmit the temperature information to the fan module. Moreover, the temperature sensor is disposed on the PCB.

Abstract: An exemplary embodiment provides a conductive connecting member, and a display device including the same, that includes a flexible elongated body and terminals formed at opposite ends of the body to be electrically connected to the body, wherein the body may include terminal areas in which the terminals are formed and a central area disposed between the terminal areas, and wherein two or more recess portions may be formed in edges of the body within the central area of the body.

Abstract: Implementations of the present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, 3D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.

Abstract: Provided is a secondary battery pack including a plurality of secondary battery modules including a plurality of secondary battery cells stacked in parallel to each other in a vertical direction, a cover, and a switch installed at an upper side of the one end in the horizontal direction of the cover, a housing, a Power Relay Assembly (PRA) including a relay electrically connected to the secondary battery cells and switches, for transmitting charging power supplied from the outside to the secondary battery cells when the relay is in a close state and changing the relay to an open state when the switch is pushed according to pressure applied to an upper side from a lower surface of the cover, and a Battery Management System (BMS) for controlling the Power Relay Assembly (PRA).