Abstract: An optical imaging system includes a first lens group including a first lens and a second lens, a second lens group including a third lens, a fourth lens, and a fifth lens, and a third lens group including a sixth lens and a seventh lens. The first to seventh lenses are arranged in order from an object side, at least one of the first lens group to the third lens group is moved on an optical axis to change a distance between the first lens group to the third lens group, and the following conditional expression is satisfied: 0.2<BFL/(2*IMG HT)<2.0 where BFL is a distance on the optical axis from an image-side surface of the seventh lens to an imaging surface of an image sensor, and IMG HT is half a diagonal length of the imaging surface of the image sensor.

Abstract: An optical imaging system includes a first lens having a convex image-side surface, a second lens having a concave object-side surface, a third lens, a fourth lens, and a fifth lens disposed sequentially from an object side. The optical imaging system satisfies 4.8<f/IMG_HT<9.0, where f is a focal length of the optical imaging system, and IMG_HT is half a diagonal length of an imaging surface of an image sensor.

Abstract: A vehicle wheel including a wavelength tube member may include spokes, a cylindrical rim configured to connect both circumferential portions of the spokes, and a wavelength tube member accommodated on the rim between the first and second circumferential portions of the spokes and configured to cancel sound wave generated in a cavity formed between the rim and a tire, wherein the wavelength tube member may include a rim seating portion being in surface-contact with and accommodated on an external surface of the rim; and a plurality of wavelength tube portions formed on the rim seating portion.

Abstract: Disclosed is a memory system includes a memory device including a plurality of memory blocks, a write operation management circuit configured to update write operation counts for the plurality of memory blocks, a first block detector configured to detect a hot memory block based on a first operation count value corresponding to the write operation count of a first memory block on which a write operation has been performed among the plurality of memory blocks, a second detector configured to detect a cold memory block based on a second operation count value corresponding to the write operation count of each of second memory blocks adjacent to the first memory block, and a controller configured to copy, if the hot memory block and the cold memory block are detected by the first and second detectors, data of the detected hot memory block or data of the detected cold memory block.

Abstract: A jig set for mounting an ESS pack, which is used to mount an ESS pack to a wall or a structure corresponding to the wall, includes: a mounting unit having a partially protruding portion capable of being coupled to one surface of an ESS pack case; and a handle unit including a handlebar to be grasped by an operator, and a locking bar, which is integrally connected to the handlebar and is attachable to and detachable from the protruding portion of the mounting unit.

Abstract: A memory system includes a memory device including one or more memory blocks, and configured to store data in a plurality of pages included in each memory block through a write operation, and a memory controller configured to count an operation number of write operations performed on the memory block, check whether the write operation is performed for each of the pages, select one or more victim pages among the pages, and copy data stored in the victim pages.

Abstract: A memory device is provided. The memory device includes a plurality of normal memory blocks; and at least two or more bad memory blocks, wherein data having the same number of bits as data to be stored in a normal memory block and a parity code having the number of bits at least twice greater than that of a parity code to be stored in the normal memory block are stored in a first bad memory block and a second bad memory block among the bad memory blocks.

Abstract: According to various embodiments, an electronic device comprises a short range communication circuit; and a processor, wherein the processor is configured to: establish a communication channel with a first external electronic device by using a designated communication scheme, through the short range communication circuit; transmit information related to the communication channel to a second external electronic device through the short range communication circuit; receive a request to transfer communication rights with the first external device to the second external device; and transfer communication rights with the first external device from the electronic device to the second external electronic device.

Abstract: An apparatus and method for identifying a short cut-in vehicle, and a vehicle using the same are disclosed. The apparatus includes a signal conversion unit configured to receive and signal-process a plurality of sensing signals, a computation unit configured to compute state information of a surrounding vehicle detected from the signal-processed signal, a sensor fusion track output unit configured to output a sensor fusion track based on the computed state information of the surrounding vehicle, an occupancy distance map (ODM) output unit configured to output ODM information including a grid map corresponding to a vehicle detection region and an ODM object including a plurality of detection points based on the computed state information of the surrounding vehicle, and a cut-in vehicle identification unit configured to identify a cut-in vehicle based on the output sensor fusion track and ODM information.

Abstract: A method for operating a memory device includes: receiving a write command; checking out whether a data strobe signal toggles or not after a given time passes from a moment when the write command is received; when the data strobe signal is checked out to be maintained at a uniform level, detecting voltage levels of a plurality of data pads; and performing an operation that is selected based on the voltage levels of the plurality of the data pads among a plurality of predetermined operations.

Abstract: A memory system comprises a memory device including a plurality of memory blocks, a write operation check unit configured to count the number of write operations performed on the respective memory blocks, a write count distribution management module configured to manage a distribution of the memory blocks based on the counted number of the write operations, and a wear leveling module configured to detect hot and cold memory blocks from the plurality of memory blocks based on the counted number of the write operation and the distribution, wherein the wear leveling module manages a history of the hot memory block and swaps the hot memory block with the cold memory block according to the managed history.

Abstract: An electronic device and method for operating the same.

Abstract: A memory system includes: a memory device; a cache memory suitable for caching a portion of a data stored in the memory device; and a read voltage controller suitable for controlling a level of a read voltage of the memory device by comparing a cache data in the cache memory with a data from the memory device corresponding to the cache data.

Abstract: A memory device includes a plurality of word lines and a plurality of bit lines intersecting the word lines, a memory cell array comprising a plurality of memory cells coupled between the word lines and the bit lines at intersections between the word lines and the bit lines, respectively, an address decoder suitable for decoding an address to access a memory cell selected among the memory cells, and a controller suitable for writing and reading data to and from the selected memory cell by applying voltages to the word lines and bit lines, wherein the controller invalidates data stored in memory cells coupled to a target word line among the word lines by applying an invalidation voltage to the target word line for a set time.

Abstract: An object recognition apparatus is disclosed. The present apparatus includes a storage unit for obtaining an initial image of a preset object and storing the initial image as a reference image; and a control unit for obtaining a first additional image of the preset object, determining whether the size of the first additional image relative to the initial image meets a first preset condition and additionally storing the first additional image as a reference image if the first additional image meets the preset condition.

Abstract: A battery module includes a cell assembly having a plurality of secondary batteries and a plurality of heat dissipation plates interposed between the plurality of secondary batteries. At least a portion of a front end and a rear end of the heat dissipation plates is recessed to form an inlet portion and an outlet portion so that a coolant is introduced from the outside or discharged to the outside, and the heat dissipation plates have a coolant moving portion so that the coolant moves to a front end, an upper end, a lower end and a rear end of the secondary batteries. A bus bar assembly has a plurality of bus bars and a bus bar frame having insert holes into which the electrode leads of the secondary batteries are inserted; an end cover having a vent hole communicating with the coolant moving portion and a plurality of side plates.

Abstract: An electronic device is provided.

Abstract: A method for operating a memory device includes: receiving a write command; checking out whether a data strobe signal toggles or not after a given time passes from a moment when the write command is received; when the data strobe signal is checked out to be maintained at a uniform level, detecting voltage levels of a plurality of data pads; and performing an operation that is selected based on the voltage levels of the plurality of the data pads among a plurality of predetermined operations.

Abstract: A method for operating a memory device includes: receiving a write command; checking out whether a data strobe signal toggles or not after a given time passes from a moment when the write command is received; when the data strobe signal is checked out to be maintained at a uniform level, detecting voltage levels of a plurality of data pads; and performing an operation that is selected based on the voltage levels of the plurality of the data pads among a plurality of predetermined operations.

Abstract: Two-terminal memory can be formed into a memory array that contains many discrete memory cells in a physical and a logical arrangement. Where each memory cell is isolated from surrounding circuitry by a single transistor, the resulting array is referred to as a 1T1R memory array. In contrast, where a group of memory cells are isolated from surrounding circuitry by a single transistor, the result is a 1TnR memory array. Because memory cells of a group are not isolated among themselves in the 1TnR case, bit disturb effects are theoretically possible when operating on a single memory cell. Read operations are disclosed for two-terminal memory devices configured to mitigate bit disturb effects, despite a lack of isolation transistors among memory cells of an array. Disclosed operations can facilitate reduced bit disturb effects even for high density two-terminal memory cell arrays.