Abstract: A memory includes: a plurality of word lines; and a row circuit configured to: activate at least one word line among the word lines to an active voltage level during an active operation and discharge the activated word line during a precharge operation; and discharge the word line from the active voltage level to a precharge voltage level in different manners during the precharge operation in response to a precharge command and during the precharge operation during a refresh operation.

Abstract: A battery module includes a sub-module stack formed by stacking a plurality of sub-modules including a cooling member having a coolant flow path and a plurality of battery cells disposed on both surfaces of the cooling member; and a pair of bus bar frame assemblies coupled to one side and the other side of the sub-module stack to electrically connect the plurality of battery cells.

Abstract: A semiconductor device includes a redundancy control signal generation circuit configured to generate a redundancy control signal by determining whether a row address for an active operation has been repaired through a soft post package repair operation and determining whether a row hammer phenomenon has occurred with respect to the row address. The semiconductor device also includes a first selection address generation circuit configured to generate a first selection address for driving a sub word line or a redundancy word line from one of a repair address and a first internal address, based on the redundancy control signal. The semiconductor device further includes a second selection address generation circuit configured to generate a second selection address for driving the sub word line or the redundancy word line from one of a fixed address and a second internal address, based on the redundancy control signal.

Abstract: A semiconductor apparatus includes a first chip that generates a first oscillator signal in response to a detection enable signal and activates a ZQ circuit in response to a ZQ enable signal, and a second chip generates the ZQ enable signal by comparing frequencies of the first oscillator signal and a second oscillator signal with each other in response to the detection enable signal.

Abstract: A semiconductor system includes a first semiconductor device and a first semiconductor device. The first semiconductor device outputs a clock, a chip selection signal and addresses. The second semiconductor device generates a masking signal from the addresses inputted in synchronization with a first pulse of the clock in response to the chip selection signal and decodes internal addresses generated from the addresses inputted in synchronization with a second pulse of the clock to select a word line. The second semiconductor device controls a connection between an address decoder and a fuse circuit in response to the masking signal. The address decoder selects the word line.

Abstract: A semiconductor system includes a first semiconductor device and a first semiconductor device. The first semiconductor device outputs a clock, a chip selection signal and addresses. The second semiconductor device generates a masking signal from the addresses inputted in synchronization with a first pulse of the clock in response to the chip selection signal and decodes internal addresses generated from the addresses inputted in synchronization with a second pulse of the clock to select a word line. The second semiconductor device controls a connection between an address decoder and a fuse circuit in response to the masking signal. The address decoder selects the word line.

Abstract: A sense amplifier includes a latch type sense unit that detects a voltage difference between a bit line and a bit line bar and causes a voltage difference between a first latch output node and a second latch output node. The sense amplifier further includes a first latch connection unit that electrically connects the bit line to and disconnects the bit line from the first latch output node.

Abstract: A semiconductor system includes a first semiconductor device and a first semiconductor device. The first semiconductor device outputs a clock, a chip selection signal and addresses. The second semiconductor device generates a masking signal from the addresses inputted in synchronization with a first pulse of the clock in response to the chip selection signal and decodes internal addresses generated from the addresses inputted in synchronization with a second pulse of the clock to select a word line. The second semiconductor device controls a connection between an address decoder and a fuse circuit in response to the masking signal. The address decoder selects the word line.

Abstract: A semiconductor apparatus includes a first chip that generates a first oscillator signal in response to a detection enable signal and activates a ZQ circuit in response to a ZQ enable signal, and a second chip generates the ZQ enable signal by comparing frequencies of the first oscillator signal and a second oscillator signal with each other in response to the detection enable signal.

Abstract: A sense amplifier includes a latch type sense unit that detects a voltage difference between a bit line and a bit line bar and causes a voltage difference between a first latch output node and a second latch output node. The sense amplifier further includes a first latch connection unit that electrically connects the bit line to and disconnects the bit line from the first latch output node.

Abstract: A semiconductor device includes a counter control signal generation circuit and an access information generation circuit. The counter control signal generation circuit generates a count enablement signal, a reset signal and a count increment signal in response to a first row address selected as a target address and a second row address selected as a neighboring address. The access information generation circuit receives the count enablement signal, the reset signal and the count increment signal to generate a first access information signal including information on the number of times that the target address is selected and a second access information signal including information on the number of times that the neighboring address is selected.

Abstract: A semiconductor device includes a latch signal generation circuit latching an external signal in synchronization with an internal clock signal to generate a latch signal, a test pulse generation circuit buffering the internal clock signal according to the latch signal to generate a test pulse signal, and a test period signal generation circuit generating a test period signal which is enabled, in response to a pulse of the test pulse signal, to execute a predetermined function.

Abstract: A semiconductor device includes a latch signal generation circuit latching an external signal in synchronization with an internal clock signal to generate a latch signal, a test pulse generation circuit buffering the internal clock signal according to the latch signal to generate a test pulse signal, and a test period signal generation circuit generating a test period signal which is enabled, in response to a pulse of the test pulse signal, to execute a predetermined function.

Abstract: A semiconductor system includes a first semiconductor device and a first semiconductor device. The first semiconductor device outputs a clock, a chip selection signal and addresses. The second semiconductor device generates a masking signal from the addresses inputted in synchronization with a first pulse of the clock in response to the chip selection signal and decodes internal addresses generated from the addresses inputted in synchronization with a second pulse of the clock to select a word line. The second semiconductor device controls a connection between an address decoder and a fuse circuit in response to the masking signal. The address decoder selects the word line.

Abstract: A semiconductor device includes a counter control signal generation circuit and an access information generation circuit. The counter control signal generation circuit generates a count enablement signal, a reset signal and a count increment signal in response to a first row address selected as a target address and a second row address selected as a neighboring address. The access information generation circuit receives the count enablement signal, the reset signal and the count increment signal to generate a first access information signal including information on the number of times that the target address is selected and a second access information signal including information on the number of times that the neighboring address is selected.

Abstract: A semiconductor device includes a flag signal generation circuit and a power-down signal generation circuit. The flag signal generation circuit generates a flag signal which is enabled in response to an operational frequency information signal. The power-down signal generation circuit generates a power-down signal for controlling input of a command in response to the flag signal and a clock enablement signal. A point of time that the power-down signal is generated is adjusted in response to the flag signal.

Abstract: A semiconductor device includes a flag signal generation circuit and a power-down signal generation circuit. The flag signal generation circuit generates a flag signal which is enabled in response to an operational frequency information signal. The power-down signal generation circuit generates a power-down signal for controlling input of a command in response to the flag signal and a clock enablement signal. A point of time that the power-down signal is generated is adjusted in response to the flag signal.