Abstract: The present invention relates to a system and method for managing Compact Component Interconnect (CPCI) buses in a multi-processing system. More particularly, the present invention improves performance and reliability of boards or systems using CPCI buses as the basic buses, by enabling all slots on a CPCI bus to function as system slots and thus obtaining the effect of parallel processing. The present invention makes it possible for all the slots on the CPCI bus of a board or system, which uses the CPCI buses as basic buses, to function as system slots. Thus, several boards of one and the same function may be applied to all the slots. As a result, the present invention improves performance through the effect of parallel processing effect may also improve the reliability through the flexible operation of the system slot over the related art.

Abstract: An apparatus for verifying memory coherency of a duplication processor having a symmetrical structure includes: an active processor in which a standby memory read command (SMRC) is generated and transmitted by hardware and then a read data of the standby memory which has been inputted corresponding to the SMRC is image-buffered to verify a memory coherency; and a standby processor in which the SMRC transmitted from the active processor is analyzed and a read command of a standby memory is outputted, and then the data read from the standby memory is transmitted to the active processor. A burst transaction can be performed both when the data is read from the standby memory and when the read data is transmitted, so that the use efficiency of the processor bus, the duplication bus and the duplication channel can be improved. Especially, a bad influence according to the operation of each processor and the duplication channel can be minimized.

Abstract: The present invention relates to a system and method for managing Compact Component Interconnect (CPCI) buses in a multi-processing system. More particularly, the present invention improves performance and reliability of boards or systems using CPCI buses as the basic buses, by enabling all slots on a CPCI bus to function as system slots and thus obtaining the effect of parallel processing. The present invention makes it possible for all the slots on the CPCI bus of a board or system, which uses the CPCI buses as basic buses, to function as system slots. Thus, several boards of one and the same function may be applied to all the slots. As a result, the present invention improves performance through the effect of parallel processing effect may also improve the reliability through the flexible operation of the system slot over the related art.

Abstract: An apparatus for verifying memory coherency of a duplication processor having a symmetrical structure includes: an active processor in which a standby memory read command (SMRC) is generated and transmitted by hardware and then a read data of the standby memory which has been inputted corresponding to the SMRC is image-buffered to verify a memory coherency; and a standby processor in which the SMRC transmitted from the active processor is analyzed and a read command of a standby memory is outputted, and then the data read from the standby memory is transmitted to the active processor. A burst transaction can be performed both when the data is read from the standby memory and when the read data is transmitted, so that the use efficiency of the processor bus, the duplication bus and the duplication channel can be improved. Especially, a bad influence according to the operation of each processor and the duplication channel can be minimized.