Abstract: A method for fabricating a semiconductor device capable of minimizing deformations of a photoresist pattern and losses of a hard mask. The method includes the steps of: forming an insulating layer for a hard mask on an etch-target layer; forming a sacrificial layer on the insulating layer; forming a photoresist pattern on the sacrificial layer; forming at least one sacrificial hard mask by etching the sacrificial layer with the photoresist pattern as an etching mask; forming the hard mask by etching the insulating layer with the sacrificial hard mask as an etching mask; and forming a predetermined number of patterns by etching the etch-target layer with use of the sacrificial hard mask and the hard mask as etching masks.

Abstract: A dual damascene process is disclosed which reduces capacitance increases caused by excess and unnecessary remnants of an etching stop layer and which also improves multi-level interconnect structures by removing the etching stop layer except for a portion that surrounds the via hole. This reduces or eliminates capacitance increase and avoids erosion of underlying interlayer insulating layers during formation of an upper, wider trench.

Abstract: An image projecting apparatus including a base, a ballast unit disposed on a top of the base, a display device disposed adjacent to the ballast unit, a cooling fan disposed on the base and introducing external air to the ballast unit, and a guide duct in communication with the ballast unit, guiding the external air blown by the cooling fan to the display device. Thus cooling down of heat generating units such as a lamp unit, a ballast unit, a colorwheel unit, etc., with a minimized number of fans is provided while reducing noise generated therefrom and increasing cooling efficiency.

Abstract: An image projecting apparatus including a base formed with a blowhole, a plurality of heat generating units disposed on a top portion of the base so as to communicate with the blowhole and generating heat when in operation, and a cooling fan disposed on a bottom of the base and cooling the plurality of heat generating units at the same time by blowing external air through the blowhole. Thus cooling down of heat generating units such as a lamp unit, a ballast unit, a colorwheel unit, etc., with a minimized number of fans is provided while reducing noise generated therefrom, and increasing cooling efficiency.

Abstract: An optical engine apparatus to magnify and project an image beam formed by a display device using light on a screen includes a light source to emit the light, a reflection mirror to reflect the light emitted from the light source toward the display device, and an adjuster coupled to the reflection mirror to adjust an inclined angle of the reflection mirror to move the light reflected from the reflection mirror toward the display device in a desired direction. In the optical engine apparatus, a position of light projected on a display device can be easily adjusted.

Abstract: A projection television includes a light source, a color wheel to selectively transmit light from the light source, an engine housing mounted with the color wheel, a color wheel housing coupled to the engine housing to accommodate the color wheel, a holder detachably coupled to the color wheel housing to rotatably support the color wheel, a coupling part to couple the holder to the color wheel housing, a first buffer provided between the holder and the color wheel housing to prevent vibration generated by the color wheel from being transmitted to the color wheel housing through the holder, a second buffer provided between the color wheel housing and the engine housing to prevent the vibration generated by the color wheel from being transmitted to the engine housing through the color wheel housing.

Abstract: A method for forming a photoresist pattern with minimally reduced transformations through the use of ArF photolithography, including the steps of: forming an organic anti-reflective coating layer on a an etch-target layer already formed on a substrate; coating a photoresist for ArF on the organic anti-reflective coating layer; exposing the photoresist with ArF laser; forming a first photoresist pattern by developing the photoresist, wherein portions of the organic anti-reflective coating layer are revealed; etching the organic anti-reflective coating layer with the first photoresist pattern as an etch mask and forming a second photoresist pattern by attaching polymer to the first photoresist pattern, wherein the polymer is generated during etching the organic anti-reflection coating layer with an etchant including O2 plasma; and etching the etch-target layer by using the second photoresist pattern as an etch mask.

Abstract: The present invention provides a method for fabricating a semiconductor device with use of an ArF light source capable of minimizing deformations of a photoresist pattern for ArF during an etching process. Also, when forming the pattern, C5F8 gas is used at a main etching step to compensate etch tolerance of the photoresist for ArF. By controlling process recipe properly, it is possible to minimize pattern deformations as simultaneously as to form a micronized pattern. To compensate the etch tolerance of the photoresist for ArF weaker than that of a photoresist for KrF, the main etching step is divided into three sub-steps, thereby providing a method for minimizing the pattern deformations when duplicating the pattern.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of first plugs contacted to a substrate by passing through a first inter-layer insulation layer; forming a second inter-layer insulation layer on the first plugs; forming a conductive pattern contacted to a group of the first plugs by etching selectively the second inter-layer insulation layer; and forming a contact hole exposing a surface of the first plug that is not contacted to the conductive pattern by etching selectively the second insulation layer with use of a dry-type and wet-type etch process, wherein an attack barrier layer is formed on between the first inter-layer insulation layer and the second inter-layer insulation layer to thereby prevent an incidence of attack to the first interlayer insulation layer contacted to the first plug during the wet-type etch process for forming the contact hole.

Abstract: A method for fabricating a semiconductor device by simultaneously forming via holes in a multi-layered structure having depth differences without requiring additional process steps. Steps to achieve this effect include forming a first conductive layer; forming a first etching protection layer on the first conductive layer; forming a first insulating layer; forming a second conductive layer on the first insulating layer; forming a second etching protection layer on the second conductive layer, wherein etching protection efficiency of the second protection layer is higher than that of the first etching protection layer; forming a second insulating layer; and forming a first and a second via hole respectively exposing the first and the second conductive layer by selectively etching the first and second insulating layer.

Abstract: The present invention relates to a method for fabricating a semiconductor device with realizable advanced fine patterns.

Abstract: A method for fabricating a semiconductor device includes the steps of: (a) forming a plurality of conductive patterns on a substrate in a cell region and a peripheral circuit region; (b) forming an insulation layer on an entire surface of the resulting structure from the step. (a); (c) forming a plurality of plugs in the cell region and simultaneously forming a dummy pattern in a region between the cell region and the peripheral circuit region, each plug and the dummy pattern being contacted to the substrate allocated between the conductive patterns by passing through the insulation layer; (d) forming a photoresist pattern masking the resulting structure in the cell region; and (e) removing the insulation layer in the peripheral circuit region by performing a wet etching process with use of the photoresist pattern as an etch mask to thereby expose a surface of the substrate in the peripheral circuit region.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of decreasing a parasitic capacitance to thereby increase a cell capacitance. To achieve this effect, the deposited third inter-layer insulation layer is planarized and is subjected to a wet etching process to make its height lower than that of the bit line. Afterwards, the nitride-based etch stop layer is formed on the etched third inter-layer insulation layer, and then, the contact hole for forming the storage node contact plug is formed in between the bit lines through the SAC process so that the etch stop layer does not remain at sidewalls of the bit line. From this structure, it is possible to decrease the parasitic capacitance, and this decrease further provides an effect of increasing the cell capacitance.

Abstract: The present invention provides a method for forming a contact plug of a semiconductor device capable of preventing an attack to conductive patterns. The method includes the steps of: forming a plurality of conductive patterns on a substrate; forming an insulating layer on top of an entire structure including the plurality of the conductive pattern; forming a contact hole by selectively etching the insulating layer; forming a conductive layer for a contact plug on the entire structure including the contact hole; forming a metal sacrificial layer on the entire structure including the conductive layer; exposing the conductive layer by performing an etchback process to the metal sacrificial layer, wherein the metal sacrificial layer is left on a lower topology area induced by the conductive patterns; and forming plugs, each being isolated by polishing the remained metal sacrificial layer, the conductive layer and the insulating layer through the use of slurry.

Abstract: A method for manufacturing a semiconductor memory device includes the steps of forming a mask layer on a target layer to be etched, coating a photoresist on the mask layer, exposing the photoresist by using a light resource whose wavelength is of about 157 nm to 193 nm, forming a photoresist pattern by developing the photoresist, forming a mask pattern by selectively etching the mask layer with an etching gas except of fluorine-based gases by using the photoresist pattern as an etching mask; and selectively etching the target layer by using the mask pattern as an etching mask.

Abstract: Provided is a method for forming a self aligned contact (SAC) of a semiconductor device that can minimize the loss of gate electrodes and hard mask. The method includes the steps of: providing a semiconductor substrate on which a plurality of conductive patterns are formed; forming a first insulation layer along the profile of the conductive patterns on the substrate; forming a second insulation layer on the substrate and simultaneously forming voids between the conductive patterns; forming a third insulation layer on the first insulation layer; and forming contact holes that expose the surface of the substrate between the conductive patterns by etching the third insulation layer and the second insulation layer covering the voids.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of first plugs contacted to a substrate by passing through a first inter-layer insulation layer; forming a second inter-layer insulation layer on the first plugs; forming a conductive pattern contacted to a group of the first plugs by etching selectively the second inter-layer insulation layer; and forming a contact hole exposing a surface of the first plug that is not contacted to the conductive pattern by etching selectively the second insulation layer with use of a dry-type and wet-type etch process, wherein an attack barrier layer is formed on between the first inter-layer insulation layer and the second inter-layer insulation layer to thereby prevent an incidence of attack to the first interlayer insulation layer contacted to the first plug during the wet-type etch process for forming the contact hole.

Abstract: An optical system includes a lens assembly fixed to a base for projecting an image light onto a surface; a DMD assembly movably disposed at one side of the lens assembly for reflecting the light irradiated from a light source onto the lens assembly; supporting members disposed at the one side of the lens assembly for supporting the DMD assembly; and an adjuster for moving the DMD assembly to adjust a tilt. The adjuster includes a guide member having a screw hole and fixed to the base; an adjusting screw driven into the screw hole for moving the DMD assembly along a lengthwise direction of the guide member; and a push rod having an end connected to the DMD assembly and another end connected to the adjusting screw. The DMD assembly is movable by adjusting the adjusting screw so that a tilt angle can be easily and precisely adjusted.

Abstract: The present invention provides a method for forming a contact plug of a semiconductor device capable of preventing an attack to conductive patterns. The method includes the steps of: forming a plurality of conductive patterns on a substrate; forming an insulating layer on top of an entire structure including the plurality of the conductive pattern; forming a contact hole by selectively etching the insulating layer; forming a conductive layer for a contact plug on the entire structure including the contact hole; forming a metal sacrificial layer on the entire structure including the conductive layer; exposing the conductive layer by performing an etchback process to the metal sacrificial layer, wherein the metal sacrificial layer is left on a lower topology area induced by the conductive patterns; and forming plugs, each being isolated by polishing the remained metal sacrificial layer, the conductive layer and the insulating layer through the use of slurry.

Abstract: The present invention provides a method for fabricating a semiconductor device with use of an ArF light source capable of minimizing deformations of a photoresist pattern for ArF during an etching process. Also, when forming the pattern, C5F8 gas is used at a main etching step to compensate etch tolerance of the photoresist for ArF. By controlling process recipe properly, it is possible to minimize pattern deformations as simultaneously as to form a micronized pattern. To compensate the etch tolerance of the photoresist for ArF weaker than that of a photoresist for KrF, the main etching step is divided into three sub-steps, thereby providing a method for minimizing the pattern deformations when duplicating the pattern.