Patents by Inventor Sang-Jib Han
Sang-Jib Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8039274Abstract: A semiconductor chip may include at least one power supply pad for receiving an external power voltage, at least one input/output pad, an internal function block that may be configured to operate based on a power voltage to at least one of receive and transmit a signal through the input/output pad, and a mode set circuit that may enable or disable the power voltage by a mode set signal in an individual chip test mode.Type: GrantFiled: April 24, 2009Date of Patent: October 18, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Sang-Jib Han
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Patent number: 7663217Abstract: Provided is a semiconductor device package. The semiconductor device package includes: stacked semiconductor chips having bonding pads; a PCB (printed circuit board) mounting the stacked semiconductor chips thereon, and including bonding electrodes that correspond to the bonding pads; and interposers respectively covering the stacked semiconductor chips and interposed between the stacked semiconductor chips. The interposers comprise wire patterns connecting the bonding pads with the bonding electrodes, and connecting the interposers to each other.Type: GrantFiled: November 6, 2007Date of Patent: February 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Jo Kim, Hyung-Lae Eun, Sang-Jib Han
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Publication number: 20090212812Abstract: A semiconductor chip may include at least one power supply pad for receiving an external power voltage, at least one input/output pad, an internal function block that may be configured to operate based on a power voltage to at least one of receive and transmit a signal through the input/output pad, and a mode set circuit that may enable or disable the power voltage by a mode set signal in an individual chip test mode.Type: ApplicationFiled: April 24, 2009Publication date: August 27, 2009Inventor: Sang-Jib Han
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Patent number: 7541612Abstract: A semiconductor chip may include at least one power supply pad for receiving an external power voltage, at least one input/output pad, an internal function block that may be configured to operate based on a power voltage to at least one of receive and transmit a signal through the input/output pad, and a mode set circuit that may enable or disable the power voltage by a mode set signal in an individual chip test mode.Type: GrantFiled: November 7, 2006Date of Patent: June 2, 2009Assignee: Sansumg Electronics Co., Ltd.Inventor: Sang-Jib Han
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Patent number: 7486532Abstract: A semiconductor multi-chip package includes: a first semiconductor memory chip having n address pads, a first control pad, and a first address controller; and a second semiconductor memory chip whose memory density is greater, e.g., at least 1.5 times greater, than the first semiconductor memory chip and which is disposed on the first semiconductor memory chip, and has (n+1) address pads, a second control pad, and a second address controller. The n address pads of the first semiconductor memory chip and the n address pads of the second semiconductor memory chip are respectively connected to corresponding n address pins. The first and second control pads are connected to a control pin. The first and second address controllers are operable in a mutually exclusive manner, e.g., manner of activation, according to a signal applied to the control pin.Type: GrantFiled: August 23, 2006Date of Patent: February 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-jib Han, Jai-kyeong Shinn
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Publication number: 20080111225Abstract: Provided is a semiconductor device package. The semiconductor device package includes: stacked semiconductor chips having bonding pads; a PCB (printed circuit board) mounting the stacked semiconductor chips thereon, and including bonding electrodes that correspond to the bonding pads; and interposers respectively covering the stacked semiconductor chips and interposed between the stacked semiconductor chips. The interposers comprise wire patterns connecting the bonding pads with the bonding electrodes, and connecting the interposers to each other.Type: ApplicationFiled: November 6, 2007Publication date: May 15, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byung-Jo KIM, Hyung-Lae EUN, Sang-Jib HAN
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Publication number: 20070108608Abstract: A semiconductor chip may include at least one power supply pad for receiving an external power voltage, at least one input/output pad, an internal function block that may be configured to operate based on a power voltage to at least one of receive and transmit a signal through the input/output pad, and a mode set circuit that may enable or disable the power voltage by a mode set signal in an individual chip test mode.Type: ApplicationFiled: November 7, 2006Publication date: May 17, 2007Inventor: Sang-Jib Han
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Publication number: 20070045827Abstract: A semiconductor multi-chip package includes: a first semiconductor memory chip having n address pads, a first control pad, and a first address controller; and a second semiconductor memory chip whose memory density is greater, e.g., at least 1.5 times greater, than the first semiconductor memory chip and which is disposed on the first semiconductor memory chip, and has (n+1) address pads, a second control pad, and a second address controller. The n address pads of the first semiconductor memory chip and the n address pads of the second semiconductor memory chip are respectively connected to corresponding n address pins. The first and second control pads are connected to a control pin. The first and second address controllers are operable in a mutually exclusive manner, e.g., manner of activation, according to a signal applied to the control pin.Type: ApplicationFiled: August 23, 2006Publication date: March 1, 2007Inventors: Sang-jib Han, Jai-kyeong Shinn
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Patent number: 7154790Abstract: Integrated circuit devices are provided including first and second chips and a common input/output pad electrically coupled to the first and second chips. At least one of the first and second chips includes a high voltage generator configured to receive an input voltage through the common input/output pad and generate a test voltage responsive to a test mode signal during a test mode of operation. The test voltage is higher than the input voltage. Related methods of operating integrated circuit devices and semiconductor devices are also provided.Type: GrantFiled: December 1, 2004Date of Patent: December 26, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Jib Han, Chang-Hwan Lee
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Publication number: 20060056248Abstract: Integrated circuit devices are provided including first and second chips and a common input/output pad electrically coupled to the first and second chips. At least one of the first and second chips includes a high voltage generator configured to receive an input voltage through the common input/output pad and generate a test voltage responsive to a test mode signal during a test mode of operation. The test voltage is higher than the input voltage. Related methods of operating integrated circuit devices and semiconductor devices are also provided.Type: ApplicationFiled: December 1, 2004Publication date: March 16, 2006Inventors: Sang-Jib Han, Chang-Hwan Lee
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Patent number: 6816429Abstract: An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory device selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory device. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory devices.Type: GrantFiled: October 9, 2002Date of Patent: November 9, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-jib Han, Du-eung Kim, Choong-keun Kwak, Yun-seung Shin
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Publication number: 20030035333Abstract: An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory device selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory device. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory devices.Type: ApplicationFiled: October 9, 2002Publication date: February 20, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-jib Han, Du-eung Kim, Choong-keun Kwak, Yun-seung Shin
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Patent number: 6510094Abstract: Disclosed is a semiconductor memory device, comprising a plurality of sub-word line drivers arranged at all memory cell array blocks in the direction of bit lines and respectively shared by two memory cell array blocks, a plurality of block sense amplifiers arranged at all memory cell array blocks in the direction of word lines and respectively shared by two memory cell array blocks, a plurality of circuit blocks respectively arranged at conjunction areas where areas accommodating sub-word line drivers and block sense amplifiers are crossed; said conjunction areas comprising one or more LA drivers adapted to drive block sense amplifiers, one or more PXiD circuits adapted to generate driving control signals to control sub-word line drivers, and-one or more BSYD circuits adapted to selectively enables LA drivers in response to transmitted block control signals; and a plurality of block control units adapted to generate upper and lower block control signals by combining column and row block address decoding signType: GrantFiled: August 28, 2001Date of Patent: January 21, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Chul Chung, Chang-Rae Kim, Sang-Jib Han, Jong-Yul Park
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Patent number: 6490223Abstract: An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory cell selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory cell. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory cells.Type: GrantFiled: July 12, 2000Date of Patent: December 3, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-jib Han, Du-eung Kim, Choong-keun Kwak, Yun-seung Shin
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Patent number: 6463002Abstract: A semiconductor memory device and method for its operation are disclosed. The memory device uses refresh-type memory cells, but operates within the same timing parameters as an SRAM. A refreshing operation and a successful read/write operation can both be performed in a read/write cycle, with zero write recovery time. But if the read/write cycle goes long, multiple refreshing operations can also be performed during the read/write cycle. Thus the device operates with no maximum write cycle time limitation. In the disclosed method, an external write command causes the device to store the write address and data to registers instead of to the memory cell array. When the external write command signals that data is present, zero write recovery time is needed, since the registers require no address setup time. Because the memory cell array is not involved in this transaction, refresh operations can proceed as needed during the external write command, no matter how long the external write takes to complete.Type: GrantFiled: March 8, 2001Date of Patent: October 8, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Rae Kim, Jong-Yul Park, Min-Chul Chung, Sang-Jib Han
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Publication number: 20020054530Abstract: Disclosed is a semiconductor memory device, comprising a plurality of sub-word line drivers arranged at all memory cell array blocks in the direction of bit lines and respectively shared by two memory cell array blocks, a plurality of block sense amplifiers arranged at all memory cell array blocks in the direction of word lines and respectively shared by two memory cell array blocks, a plurality of circuit blocks respectively arranged at conjunction areas where areas accommodating sub-word line drivers and block sense amplifiers are crossed; said conjunction areas comprising one or more LA drivers adapted to drive block sense amplifiers, one or more PXiD circuits adapted to generate driving control signals to control sub-word line drivers, and one or more BSYD circuits adapted to selectively enables LA drivers in response to transmitted block control signals; and a plurality of block control units adapted to generate upper and lower block control signals by combining column and row block address decoding signType: ApplicationFiled: August 28, 2001Publication date: May 9, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: Min-Chul Chung, Chang-Rae Kim, Sang-Jib Han, Jong-Yul Park
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Publication number: 20020001247Abstract: A semiconductor memory device and method for its operation are disclosed. The memory device uses refresh-type memory cells, but operates within the same timing parameters as an SRAM. A refreshing operation and a successful read/write operation can both be performed in a read/write cycle, with zero write recovery time. But if the read/write cycle goes long, multiple refreshing operations can also be performed during the read/write cycle. Thus the device operates with no maximum write cycle time limitation.Type: ApplicationFiled: March 8, 2001Publication date: January 3, 2002Applicant: Samsung ElectronicsInventors: Chang-Rae Kim, Jong-Yul Park, Min-Chul Chung, Sang-Jib Han
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Patent number: 6288926Abstract: A semiconductor memory device is disclosed. The device is comprised of a plurality of word lines; a plurality of bit lines arranged in perpendicular to the word lines. In addition, a plurality of supply voltage lines extend in the same direction as the bit lines. Also, a plurality of first ground voltage lines are arranged in the same direction as the bit lines. Further, a plurality of second ground voltage lines are arranged in the same direction as the word lines. A plurality of memory cells are each connected between one of the word lines and one of the bit lines. Here, the ground voltage lines are arranged in a matrix shape to reduce the resistance of the ground voltage line and secure the margin between the supply voltage level and the ground voltage level of the data latched by the memory cells to thereby prevent an operational failure of the device.Type: GrantFiled: March 27, 2000Date of Patent: September 11, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Du-Eung Kim, Byung-Gil Choi, Sang-Jib Han, Choong-Keun Kwak, Soon-Moon Jung, Sung-Bong Kim
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Patent number: 6275437Abstract: A semiconductor memory device and method for its operation are disclosed. The memory device uses refresh-type memory cells, but operates within the same timing parameters as a SRAM. A refreshing operation and a successful read/write operation can both be performed in a read/write cycle, with zero write recovery time. But if the read/write cycle goes long, multiple refreshing operations can also be performed during the read/write cycle. Thus the device operates with no maximum write cycle time limitation. In the disclosed method, an external write command causes the device to store the write address and data to registers instead of to the memory cell array. When the external write command signals that data is present, zero write recovery time is needed, since the registers require no address setup time. Because the memory cell array is not involved in this transaction, refresh operations can proceed as needed during the external write command, no matter how long the external write takes to complete.Type: GrantFiled: June 30, 2000Date of Patent: August 14, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Rae Kim, Jong-Yul Park, Min-Chul Chung, Sang-Jib Han
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Patent number: 6271705Abstract: A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.Type: GrantFiled: November 22, 1999Date of Patent: August 7, 2001Assignee: Samsung Electronics Co., LtdInventors: Young-Ho Suh, Choong-Keun Kwak, Sang-Jib Han