Abstract: Disclosed is a method of controlling a server for managing movement schedules of a plurality of robots. The control method includes receiving an occupancy request for at least one node matching a scheduled moving route from at least one of the plurality of robots; setting actually occupied nodes and provisionally occupied nodes of each of the plurality of robots based on the occupancy request; and transmitting occupancy permission information including the set actually occupied node and provisionally occupied node to each of the plurality of robots. In the setting of the actually occupied node and the provisionally occupied node, the actually occupied nodes and the provisionally occupied nodes of each of the plurality of robots are selected so that an actually occupied node of one robot does not overlap an actually occupied node or a provisionally occupied node of another robot.

Abstract: An operating method of a memory device, comprising: entering self-refresh section, updating a counting code by counting an edge of a reference cycle signal, first activating an operation control signal for the self-refresh section when a temperature application code has an initialized value in response to the counting code, updating the temperature application code after the operation control signal is first activated, second activating the operation control signal in response to the counting code based on the updated temperature application code, exiting from the self-refresh section, and initializing the counting code and the temperature application code.

Abstract: A method for operating a memory includes: receiving a predetermined command; performing an error check operation on a selected row and selected columns of one memory bank among a plurality of memory banks in response to the predetermined command; and performing a refresh operation on a selected row of each of the other memory banks among the memory banks in response to the predetermined command.

Abstract: Provided is an electric seat control apparatus for a vehicle including: a first rail and a second rail mounted at a constant interval on the floor surface of a vehicle body in the forward and rearward directions of a seat; a first movement unit provided with a first motor and mounted between the first rail and the lower surface of the seat to move linearly along the first rail; a second movement unit provided with a second motor and mounted between the second rail and the lower surface of the seat to move linearly along the second rail; and a control unit that simultaneously receives the RPM and a rotational position signal of the first motor and the RPM and a rotational position signal of the second motor to synchronize the RPMs and rotational positions of the first motor and the second motor to match each other.

Abstract: A semiconductor apparatus includes a chip ID generation unit, a chip ID transmission unit and a chip stack information generation unit. The chip ID generation unit is configured to generate a chip ID signal. The chip ID transmission unit is configured to output the chip ID signal to a common line on the basis of whether another chip is electrically coupled therewith. The chip stack information generation unit is configured to be electrically coupled with the common line in response to the chip ID signal and generate a stack information signal.

Abstract: A semiconductor module may include a host, a first semiconductor device, and a second semiconductor device. The first host line may be connected to the first and second semiconductor device or devices, according to a set mode.

Abstract: A system includes: a master device; and a slave device including a temperature variation measuring circuit for measuring a temperature variation amount of the salve device for a predetermined time. The slave device transfers temperature information to a master device when a temperature variation amount for the predetermined time is equal to or greater than a threshold value, the temperature information representing that the temperature variation amount for the predetermined time is equal to or greater than the threshold value. The master device determines a temperature of the slave device in response to the temperature information, and controls the slave device based on the determined temperature of the slave device.

Abstract: A memory system includes: a memory device including a plurality of memory banks; and a memory controller suitable for monitoring a workload of the memory device and applying one of a first refresh command and a second refresh command to the memory device according to a result of the monitoring. In the memory device, the number of memory banks to be refreshed by the second refresh command may be greater than the number of memory banks to be refreshed by the first refresh command.

Abstract: A system includes: a master device; and a slave device including a temperature variation measuring circuit for measuring a temperature variation amount of the salve device for a predetermined time. The slave device transfers temperature information to a master device when a temperature variation amount for the predetermined time is equal to or greater than a threshold value, the temperature information representing that the temperature variation amount for the predetermined time is equal to or greater than the threshold value. The master device determines a temperature of the slave device in response to the temperature information, and controls the slave device based on the determined temperature of the slave device.

Abstract: A signal transmitting circuit may include: a logic gate coupled in series to transmit a signal, and operated by a first supply voltage; a pre-driver circuit suitable for generating a pull-up control signal and a pull-down control signal in response to the transmitted signal, wherein a second supply voltage having a level greater than the target level of the first supply voltage is used to generate the pull-up and pull-down control signals; a first NMOS transistor suitable for pulling up an output node using the first supply voltage, in response to the pull-up control signal; a second NMOS transistor suitable for pulling down the output node using a pull-down voltage, in response to the pull-down control signal; and an initialization circuit suitable for initializing the pull-up and pull-down control signals when the level of the first supply voltage is less than a reference value, before a power-up signal is enabled.

Abstract: A semiconductor module may include a host, a first semiconductor device, and a second semiconductor device. The first host line may be connected to the first and second semiconductor device or devices, according to a set mode.

Abstract: A semiconductor package includes: memory devices that are stacked one on another; and an inter-layer channel for communication between the memory devices, wherein each memory device includes: a data pad; a memory core; a data input/output circuit that inputs/outputs data through the data pad; an inter-layer channel transfer circuit that transfers a read data transferred from the memory core to the inter-layer channel or transfers a data inputted through the data input/output circuit to the inter-layer channel; an inter-layer channel reception circuit receiving the data of the inter-layer channel; a read error correction circuit correcting an error of the data transferred from the inter-layer channel reception circuit to produce an error-corrected data and transfers the error-corrected data to the data input/output circuit; and a write error correction circuit generating a parity data to be stored in the memory core based on the data transferred from the inter-layer channel reception circuit.

Abstract: A memory device includes a normal cell array, a parity cell array, and a plurality of normal write drivers suitable for writing normal write data in the normal cell array. The memory device also includes a plurality of parity write drivers suitable for writing parity write data corresponding to the normal write data, in the parity cell array, and an error injection circuit suitable for injecting error write data to at least one among the plurality of the normal write drivers and the plurality of the parity write drivers to exactly analyze an error of the memory device.

Abstract: A memory device includes: a normal cell array; a parity cell array; a plurality of normal write drivers suitable for writing normal write data in the normal cell array; a plurality of parity write drivers suitable for writing parity write data corresponding to the normal write data, in the panty cell array; and an error injection circuit suitable for injecting error write data to at least one among the plurality of the normal write drivers and the plurality of the parity write drivers.

Abstract: A semiconductor apparatus includes a chip ID generation unit, a chip ID transmission unit and a chip stack information generation unit. The chip ID generation unit is configured to generate a chip ID signal. The chip ID transmission unit is configured to output the chip ID signal to a common line on the basis of whether another chip is electrically coupled therewith. The chip stack information generation unit is configured to be electrically coupled with the common line in response to the chip ID signal and generate a stack information signal.

Abstract: A semiconductor package includes: memory devices that are stacked one on another; and an inter-layer channel for communication between the memory devices, wherein each memory device includes: a data pad; a memory core; a data input/output circuit that inputs/outputs data through the data pad; an inter-layer channel transfer circuit that transfers a read data transferred from the memory core to the inter-layer channel or transfers a data inputted through the data input/output circuit to the inter-layer channel; an inter-layer channel reception circuit receiving the data of the inter-layer channel; a read error correction circuit correcting an error of the data transferred from the inter-layer channel reception circuit to produce an error-corrected data and transfers the error-corrected data to the data input/output circuit; and a write error correction circuit generating a parity data to be stored in the memory core based on the data transferred from the inter-layer channel reception circuit.

Abstract: A semiconductor apparatus may include a master chip, first to nth slave chips, first to nth slave chip ID generating units, and a master chip ID generating unit. The first to nth slave chip ID generating units are disposed respectively in the first to nth slave chips and connected in series to each other. Each of the first to nth slave chip ID generating units is configured to add a predetermined code value to an mth operation code to generate an (m+1)th operation code. The master chip ID generating unit is disposed in the master chip to generate a variable first operation code in response to a select signal. Here, ‘n’ is an integer that is equal to or greater than 2, and ‘m’ is an integer that is equal to or greater than 1 and equal to or smaller than ‘n’.

Abstract: A semiconductor apparatus includes a chip ID generation unit, a chip ID transmission unit and a chip stack information generation unit. The chip ID generation unit is configured to generate a chip ID signal. The chip ID transmission unit is configured to output the chip ID signal to a common line on the basis of whether another chip is electrically coupled therewith. The chip stack information generation unit is configured to be electrically coupled with the common line in response to the chip ID signal and generate a stack information signal.

Abstract: A system includes: a master device; and a slave device including a temperature variation measuring circuit for measuring a temperature variation amount of the salve device for a predetermined time. The slave device transfers temperature information to a master device when a temperature variation amount for the predetermined time is equal to or greater than a threshold value, the temperature information representing that the temperature variation amount for the predetermined time is equal to or greater than the threshold value. The master device determines a temperature of the slave device in response to the temperature information, and controls the slave device based on the determined temperature of the slave device.

Abstract: A memory system includes: a memory device including a plurality of memory banks; and a memory controller suitable for monitoring a workload of the memory device and applying one of a first refresh command and a second refresh command to the memory device according to a result of the monitoring. In the memory device, the number of memory banks to be refreshed by the second refresh command may be greater than the number of memory banks to be refreshed by the first refresh command.