Abstract: Provided is an Inductor-Capacitor (LC) quadrature Voltage Controlled Oscillator (VCO) having a startup circuit which can accurately select one of +90° and ?90° as a phase difference between two clocks generated by the LC quadrature VCO by embodying the startup circuit therein by using a phase detector and a controller.

Abstract: Provided is a replica bias circuit which is suitable for multi-layer stacked CMOS current mode logic (CML) and is stably used in application fields using a low power supply voltage. The replica bias circuit applies a reference voltage to gates of target transistors constituting an electronic circuit. The replica bias circuit includes a sub threshold voltage generator for maintaining a voltage difference lower than a threshold voltage of the transistor; and a replica path including devices designed by referring to dimensions of constituent devices forming a current flow path, the current flow path including the target transistors in the electronic circuit. With the replica bias circuit, multi-layer stacked CMOS current mode logic (CML) circuits can stably operate even at a low power supply voltage.

Abstract: Provided is a quadrature voltage controlled oscillator having only one resonant mode characteristic. The quadrature voltage controlled oscillator has a structure in which two clocks generated from respective LC resonant circuits are 90 degrees out of phase with each other using a phase detector and a loop filter, instead of a general structure in which two LC tank resonant circuits are mutually coupled to constitute an LC quadrature voltage controlled oscillator. The quadrature voltage controlled oscillator includes two resonant circuits having the same oscillation frequency; and a phase controller receiving oscillation clocks of the two resonant circuits to control at least one of oscillation phases of the two resonant circuits according to a phase difference between the two oscillation clocks.

Abstract: Provided is an Inductor-Capacitor (LC) quadrature Voltage Controlled Oscillator (VCO) having a startup circuit which can accurately select one of +90° and ?90° as a phase difference between two clocks generated by the LC quadrature VCO by embodying the startup circuit therein by using a phase detector and a controller.

Abstract: Provided are a layout method of a power line for a semiconductor integrated circuit and a semiconductor integrated circuit manufactured by the layout method. The layout method includes the steps of: forming a decoupling capacitor on a substrate; laying out a first metal layer, connected to the decoupling capacitor through a contact, above a region where the decoupling capacitor is formed so as to cover the decoupling capacitor; and laying out a second metal layer above a region where the first metal layer is formed. Therefore, the metal layers and the decoupling capacitor are laid out in the same region so that a chip area can be prevented from being additionally consumed at the time of laying out the decoupling capacitor, and degradation which may occur due to connection line resistance from the power lines to the decoupling capacitors can be prevented.

Abstract: The present invention relates to a method for preparing germinated brown rice that has better texture, is easier to cook and has higher safety from microbial contamination compared with conventional germinated brown rice, by controlling the conditions for the germination process, and to a germinated brown rice obtained therefrom. More particularly, improved germinated brown rice can be obtained by at least partially removing the skin, germinating the altered rice in slighted acid germination water and treating the germinated brown rice at elevated temperatures and pressures.

Abstract: A system and method are disclosed for providing a FSK demodulator using DLL and a demodulating method which detects a time order of the rising edges of square waves that correspond to two modulation frequencies and an in-between frequency and demodulates the relevant frequencies into data. The FSK demodulator includes a band-pass filter, an amplitude limiter for converting a waveform of the frequency filtered into a square wave, a delay line for receiving the square wave from the amplitude limiter and delaying the square wave for a delay time, a delayed flip-flop (DFF) for receiving an output signal from the amplitude limiter and an output signal from the delay line, determining which rising edge of the two input signals is earlier at a given time, and outputting the result of the determination as data, and a DLL circuit that locks the delay time of the delay line.

Abstract: A clock and data recovery apparatus reduces current consumption and enables easy integration. The inventive apparatus includes a first loop including a frequency/phase detection unit, a first charge pump unit, a multiplexing unit, a filtering unit, and a voltage controlled oscillator unit operating at a speed ¼ as fast as that of received data; a second loop having a phase detection unit operating at a speed ¼ as fast as a speed of received data, a second charge pump unit suitable for the phase detection unit, the multiplexing unit, the filtering unit, and the voltage controlled oscillator unit; a frequency lock detection unit for judging whether a frequency of a feedback clock signal falls within a desired frequency range; and a data recovery unit for recovering data from received data.

Abstract: Provided is a frequency lock detector which includes one counter and a clock number difference detector for detecting a clock number difference while not increasing complexity according to the counting number N to compare the frequencies of two clock signals whose phases are not synchronous to each other and determine whether the difference between the frequencies of the two signals is within a desired frequency accuracy. The frequency lock detector includes: a counter for counting the number of clocks of a reference clock signal inputted from outside; a clock number difference detector for detecting a difference between the clock number of the reference clock signal and the clock number of a recovered clock signal whose phase is not synchronous to the phase of the reference clock signal; and a lock determiner for determining a frequency lock based on result values of the counter and the clock number difference detector.

Abstract: A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

Abstract: A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.

Abstract: The present invention relates to a method for preparing germinated brown rice that has better texture, is easier to cook and has higher safety from microbial contamination compared with conventional germinated brown rice, by controlling the conditions for the germination process, and to a germinated brown rice obtained therefrom. More particularly, improved germinated brown rice can be obtained by at least partially removing the skin, germinating the altered rice in slighted acid germination water and treating the germinated brown rice at elevated temperatures and pressures.

Abstract: A system and method are disclosed for providing a FSK demodulator using DLL and a demodulating method which detects a time order of the rising edges of square waves that correspond to two modulation frequencies and an in-between frequency and demodulates the relevant frequencies into data. The FSK demodulator includes a band-pass filter, an amplitude limiter for converting a waveform of the frequency filtered into a square wave, a delay line for receiving the square wave from the amplitude limiter and delaying the square wave for a delay time, a delayed flip-flop (DFF) for receiving an output signal from the amplitude limiter and an output signal from the delay line, determining which rising edge of the two input signals is earlier at a given time, and outputting the result of the determination as data, and a DLL circuit that locks the delay time of the delay line.

Abstract: A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

Abstract: A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.