Patents by Inventor Sang-Koo KANG
Sang-Koo KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220069092Abstract: A semiconductor device may include first and second fin-shaped patterns on a substrate, that extend in a first direction, and are spaced apart from each other in a second direction. A first epitaxial pattern may be on the first fin-shaped pattern, and a second epitaxial pattern may be on the second fin-shaped pattern. A field insulating layer may be on the substrate, and may cover a sidewall of the first fin-shaped pattern, a sidewall of the second fin-shaped pattern, a part of a sidewall of the first epitaxial pattern, and a part of a sidewall of the second epitaxial pattern. The top surface of the field insulating layer may be higher than the bottom surface of the first epitaxial pattern and the bottom surface of the second epitaxial pattern.Type: ApplicationFiled: March 30, 2021Publication date: March 3, 2022Inventors: Sun Ki Min, Chae Ho Na, Sang Koo Kang, Ik Soo Kim, Dong Hyun Roh
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Patent number: 11004732Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively; forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region; forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including first colloid; and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.Type: GrantFiled: June 27, 2019Date of Patent: May 11, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-ki Min, Koung-min Ryu, Sung-soo Kim, Sang-koo Kang
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Patent number: 10818657Abstract: There is provided a semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer using a hybrid interlayer insulating film. The semiconductor device includes a gate electrode on a substrate, a gate spacer being on a sidewall of the gate electrode and including an upper portion and a lower portion, a lower interlayer insulating film being on the substrate and overlapping with the lower portion of the gate spacer, and an upper interlayer insulating film being on the lower interlayer insulating film and overlapping with the upper portion of the gate spacer, wherein the lower interlayer insulating film is not interposed between the upper interlayer insulating film and the upper portion of the gate spacer.Type: GrantFiled: August 10, 2016Date of Patent: October 27, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-Ki Min, Koung-Min Ryu, Sang-Koo Kang
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Patent number: 10580891Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.Type: GrantFiled: November 16, 2018Date of Patent: March 3, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Soo Kim, Gi-Gwan Park, Sang-Koo Kang, Koung-Min Ryu, Jae-Hoon Lee, Tae-Won Ha
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Publication number: 20190318961Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively, forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region, forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including a first colloid, and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.Type: ApplicationFiled: June 27, 2019Publication date: October 17, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-ki Min, Koung-min Ryu, Sung-soo Kim, Sang-koo Kang
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Patent number: 10381265Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively, forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region, forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including a first colloid, and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.Type: GrantFiled: May 8, 2017Date of Patent: August 13, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-ki Min, Koung-min Ryu, Sung-soo Kim, Sang-koo Kang
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Publication number: 20190088779Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.Type: ApplicationFiled: November 16, 2018Publication date: March 21, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-Soo KIM, Gi-Gwan PARK, Sang-Koo KANG, Koung-Min RYU, Jae-Hoon LEE, Tae-Won HA
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Patent number: 10177253Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.Type: GrantFiled: October 11, 2016Date of Patent: January 8, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Soo Kim, Gi-Gwan Park, Sang-Koo Kang, Koung-Min Ryu, Jae-Hoon Lee, Tae-Won Ha
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Patent number: 10128240Abstract: A semiconductor device includes a substrate including first to third regions, wherein the third region is positioned in a first direction between the first and second regions, a fin protruding on the substrate and extending in the first direction, first and second gate structures respectively formed on the fin in the first and second regions, first and second spacers formed with spacing apart from each other on the fin in the third region. The first and second spacers are sloped in a direction away from each other, and the first and second spacers and an upper surface of the fin define a plurality of acute angles, the first and second spacers defining a recess, the fin and the first and second spacers defining sidewalls of the recess, and a device isolating film substantially filling the recess.Type: GrantFiled: November 8, 2017Date of Patent: November 13, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sun Ki Min, Sang Koo Kang, Koung Min Ryu, Gi Gwan Park
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Publication number: 20180138174Abstract: A semiconductor device includes a substrate including first to third regions, wherein the third region is positioned in a first direction between the first and second regions, a fin protruding on the substrate and extending in the first direction, first and second gate structures respectively formed on the fin in the first and second regions, first and second spacers formed with spacing apart from each other on the fin in the third region. The first and second spacers are sloped in a direction away from each other, and the first and second spacers and an upper surface of the fin define a plurality of acute angles, the first and second spacers defining a recess, the fin and the first and second spacers defining sidewalls of the recess, and a device isolating film substantially filling the recess.Type: ApplicationFiled: November 8, 2017Publication date: May 17, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Sun Ki MIN, Sang Koo Kang, Koung Min Ryu, Gi Gwan Park
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Publication number: 20170345712Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively, forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region, forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including a first colloid, and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.Type: ApplicationFiled: May 8, 2017Publication date: November 30, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-ki MIN, Koung-min RYU, Sung-soo KIM, Sang-koo KANG
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Publication number: 20170117192Abstract: A semiconductor device may include a first gate electrode being formed on a substrate and having a first ratio of a width of an upper surface to a width of a lower surface, a second gate electrode being formed on the substrate and having a second ratio of the width of the upper surface to the width of the lower surface, wherein the second ratio is less than the first ratio, a first gate spacer being formed on a sidewall of the first gate electrode, a second gate spacer being formed on a sidewall of the second gate electrode and an interlayer insulating film covering the first gate spacer and the second gate spacer.Type: ApplicationFiled: July 21, 2016Publication date: April 27, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-Ki Min, Gi-Gwan PARK, Sang-Koo KANG, Sung-Sao KIM, Ju-Youn KIM, Koung-Min RYU, Jae-Hoon LEE, Tae-Won HA
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Publication number: 20170110576Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.Type: ApplicationFiled: October 11, 2016Publication date: April 20, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-Soo KIM, Gi-Gwan PARK, Sang-Koo KANG, Koung-Min RYU, Jae-Hoon LEE, Tae-Won HA
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Publication number: 20170053913Abstract: There is provided a semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer using a hybrid interlayer insulating film. The semiconductor device includes a gate electrode on a substrate, a gate spacer being on a sidewall of the gate electrode and including an upper portion and a lower portion, a lower interlayer insulating film being on the substrate and overlapping with the lower portion of the gate spacer, and an upper interlayer insulating film being on the lower interlayer insulating film and overlapping with the upper portion of the gate spacer, wherein the lower interlayer insulating film is not interposed between the upper interlayer insulating film and the upper portion of the gate spacer.Type: ApplicationFiled: August 10, 2016Publication date: February 23, 2017Inventors: Sun-Ki MIN, Koung-Min RYU, Sang-Koo KANG