Patents by Inventor Sang-Kyoung Lee
Sang-Kyoung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240156944Abstract: The present invention relates to an attenuated reovirus-based vaccine composition and a use thereof, the attenuated reovirus, according to the present invention, having the 251st to 455th amino acids of a sigma-1 protein of a capsid truncated such that when an epitope of an antigenic protein inducing cancer or infectious disease is introduced to the truncated site of the sigma-1 protein, the epitope of the antigenic protein is stably expressed in a cell, and thus the effect is gained of exhibiting an immune response such as producing a neutralizing antibody or inducing cell-mediated immunity. As such, the present invention is expected to be usefully employable as a vaccine composition for cancer or infectious disease by introducing the epitope of the antigenic protein to the truncated site of the sigma-1 protein of the attenuated reovirus according to the present invention.Type: ApplicationFiled: March 22, 2022Publication date: May 16, 2024Inventors: Haeng Jun YOO, Tommy Michel ALAIN, Sang Kyoung HAN, Xiao XIANG, So Young KIM, Yeon Sook LEE, Ki Hoon SONG
-
Publication number: 20240121996Abstract: A display device is provided. The display device includes a substrate including a display area and a pad area, which is disposed on one side of the display area, a plurality of conductive layers disposed on the substrate, in the display area and the pad area, a passivation layer disposed on the conductive layers, and a plurality of light-emitting elements disposed on the passivation layer, in the display area, and spaced apart from one another, wherein at least one of the conductive layers includes a first metal layer, a second metal layer, which is disposed on the first metal layer, and a third metal layer, which is disposed on the second metal layer, the first metal layer includes vanadium (V), the second metal layer includes aluminum (Al) or an Al alloy, and the third metal layer includes V or titanium (Ti).Type: ApplicationFiled: July 31, 2023Publication date: April 11, 2024Inventors: Hyun Eok SHIN, Sang Gab KIM, Joon Yong PARK, Do Keun SONG, Su Kyoung YANG, Dong Min LEE
-
Publication number: 20240066960Abstract: An embodiment vehicle door opening/closing system includes an inner panel defining a door open portion of a vehicle, the inner panel including an installation groove having a protruding or recessed shape, a driving device disposed in the installation groove of the inner panel, and a link mechanism installed on a chassis through a rotating shaft, a first end of the link mechanism being connected to the driving device such that power is transferred thereto, and a second end of the link mechanism being connected to a door such that, during driving of the driving device, the link mechanism rotates with reference to the rotating shaft to open/close the door.Type: ApplicationFiled: January 23, 2023Publication date: February 29, 2024Inventors: Chang Hak Kang, Jae Seung Lee, Gook Hyun Jeon, Chan Woong Jeon, Sang Kyoung Han, Hae Hoon Lee
-
Patent number: 8749362Abstract: An apparatus and method for synchronizing a sound source and a vibration generated according to a user's touch input in order to implement a haptic function in a portable terminal are provided. The apparatus includes a response processor for synchronizing a time when a vibration is generated and a time when a sound source is generated by regulating a time when a vibration request signal is generated.Type: GrantFiled: November 30, 2010Date of Patent: June 10, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Kyoung Lee, Jae-Kwang Han
-
Patent number: 8431983Abstract: A non-volatile memory device and a method of fabricating the same are provided. The method can include disposing an isolation layer on a semiconductor substrate. The isolation layer may protrude from the main surface of the semiconductor substrate and define an active region. In a recess defined by the protrusion of the isolation layer and the active region, a diffusion-retarding poly pattern and a floating gate may be formed in sequence. A control gate may be disposed on the isolation layer to cover the diffusion-retarding poly pattern and the floating gate.Type: GrantFiled: December 30, 2009Date of Patent: April 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Woong Lee, Jung-Yoon Ko, Sang-Kyoung Lee, Ho-Min Son, Won-Jun Jang, Jung-Geun Jee
-
Patent number: 8310262Abstract: A plurality of gate lines are formed on an insulating substrate in the horizontal direction, a gate shorting bar connected to the data lines is formed in the vertical direction and a gate insulating film is formed thereon. A plurality of data lines intersecting the gate lines are formed on the gate insulating film in the vertical direction, and a data shorting bar connected to the data lines is formed outside the display region. A first shorting bar is formed on the gate insulating film, located between the gate lines and the gate shorting bar, and connected to the odd gate lines. A second secondary shorting bar is formed parallel to the first shorting bar and connected to the even gate lines.Type: GrantFiled: October 22, 2009Date of Patent: November 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Kyoung Lee, Dong-Gyu Kim, Min-Hyung Moon
-
Publication number: 20110128134Abstract: An apparatus and method for synchronizing a sound source and a vibration generated according to a user's touch input in order to implement a haptic function in a portable terminal are provided. The apparatus includes a response processor for synchronizing a time when a vibration is generated and a time when a sound source is generated by regulating a time when a vibration request signal is generated.Type: ApplicationFiled: November 30, 2010Publication date: June 2, 2011Applicant: SAMSUNG ELECTRONICS CO. LTD.Inventors: Sang-Kyoung LEE, Jae-Kwang HAN
-
Publication number: 20100171166Abstract: A non-volatile memory device and a method of fabricating the same are provided. The method can include disposing an isolation layer on a semiconductor substrate. The isolation layer may protrude from the main surface of the semiconductor substrate and define an active region. In a recess defined by the protrusion of the isolation layer and the active region, a diffusion-retarding poly pattern and a floating gate may be formed in sequence. A control gate may be disposed on the isolation layer to cover the diffusion-retarding poly pattern and the floating gate.Type: ApplicationFiled: December 30, 2009Publication date: July 8, 2010Inventors: Woong Lee, Jung-Yoon Ko, Sang-Kyoung Lee, Ho-Min Son, Won-Jun Jang, Jung-geun Jee
-
Publication number: 20100039119Abstract: A plurality of gate lines are formed on an insulating substrate in the horizontal direction, a gate shorting bar connected to the data lines is formed in the vertical direction and a gate insulating film is formed thereon. A plurality of data lines intersecting the gate lines are formed on the gate insulating film in the vertical direction, and a data shorting bar connected to the data lines is formed outside the display region. A first shorting bar is formed on the gate insulating film, located between the gate lines and the gate shorting bar, and connected to the odd gate lines. A second secondary shorting bar is formed parallel to the first shorting bar and connected to the even gate lines.Type: ApplicationFiled: October 22, 2009Publication date: February 18, 2010Inventors: Sang-Kyoung LEE, Dong-Gyu Kim, Min-Hyung Moon
-
Patent number: 7626414Abstract: A plurality of gate lines are formed on an insulating substrate in the horizontal direction, a gate shorting bar connected to the data lines is formed in the vertical direction and a gate insulating film is formed thereon. A plurality of data lines intersecting the gate lines are formed on the gate insulating film in the vertical direction, and a data shorting bar connected to the data lines is formed outside the display region. A first shorting bar is formed on the gate insulating film, located between the gate lines and the gate shorting bar, and connected to the odd gate lines. A second secondary shorting bar is formed parallel to the first shorting bar and connected to the even gate lines.Type: GrantFiled: October 13, 2008Date of Patent: December 1, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Kyoung Lee, Dong-Gyu Kim, Min-Hyung Moon
-
Patent number: 7579237Abstract: A method of manufacturing a nonvolatile memory device includes forming a plurality of device isolation regions in a semiconductor substrate, forming a tunneling insulation layer on the semiconductor substrate, forming a first preliminary polysilicon layer in communication with the tunneling insulation layer and the device isolation regions, forming a preliminary amorphous silicon layer on the first preliminary silicon layer, forming a second preliminary polysilicon layer on the preliminary amorphous silicon layer, and patterning the second preliminary polysilicon layer, the preliminary amorphous silicon layer, and the first preliminary polysilicon layer to form a floating gate layer.Type: GrantFiled: January 16, 2007Date of Patent: August 25, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Kyoung Lee, Jin-Hong Kim, Dong-Hwan Kim, Won-Sik Shin, Woong Lee
-
Publication number: 20090039348Abstract: A plurality of gate lines are formed on an insulating substrate in the horizontal direction, a gate shorting bar connected to the data lines is formed in the vertical direction and a gate insulating film is formed thereon. A plurality of data lines intersecting the gate lines are formed on the gate insulating film in the vertical direction, and a data shorting bar connected to the data lines is formed outside the display region. A first shorting bar is formed on the gate insulating film, located between the gate lines and the gate shorting bar, and connected to the odd gate lines. A second secondary shorting bar is formed parallel to the first shorting bar and connected to the even gate lines.Type: ApplicationFiled: October 13, 2008Publication date: February 12, 2009Inventors: Sang-Kyoung LEE, Dong-Gyu Kim, Min-Hyung Moon
-
Patent number: 7446556Abstract: A plurality of gate lines are formed on an insulating substrate in the horizontal direction, a gate shorting bar connected to the data lines is formed in the vertical direction and a gate insulating film is formed thereon. A plurality of data lines intersecting the gate lines are formed on the gate insulating film in the vertical direction, and a data shorting bar connected to the data lines is formed outside the display region. A first shorting bar is formed on the gate insulating film, located between the gate lines and the gate shorting bar, and connected to the odd gate lines. A second secondary shorting bar is formed parallel to the first shorting bar and connected to the even gate lines.Type: GrantFiled: July 24, 2006Date of Patent: November 4, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Kyoung Lee, Dong-Gyu Kim, Min-Hyung Moon
-
Patent number: 7410869Abstract: In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the insulating pattern. The first silicon layer has an opened seam overlying the previously exposed portion of the substrate. A heat treatment on the substrate is performed at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed via the silicon migration. A second silicon layer is then formed on the first silicon layer. Thus, surface profile of a floating gate electrode obtained from the first and second silicon layers may be improved.Type: GrantFiled: July 5, 2006Date of Patent: August 12, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hun-Hyeoung Leam, Hyeon-Deok Lee, Young-Sub You, Won-Jun Jang, Woong Lee, Jung-Hyun Park, Sang-Kyoung Lee, Jung-Geun Jee, Sang-Hoon Lee
-
Publication number: 20080090352Abstract: A method of manufacturing a nonvolatile memory device includes forming a plurality of device isolation regions in a semiconductor substrate, forming a tunneling insulation layer on the semiconductor substrate, forming a first preliminary polysilicon layer in communication with the tunneling insulation layer and the device isolation regions, forming a preliminary amorphous silicon layer on the first preliminary silicon layer, forming a second preliminary polysilicon layer on the preliminary amorphous silicon layer, and patterning the second preliminary polysilicon layer, the preliminary amorphous silicon layer, and the first preliminary polysilicon layer to form a floating gate layer.Type: ApplicationFiled: January 16, 2007Publication date: April 17, 2008Inventors: Sang-Kyoung Lee, Jin-Hong Kim, Dong-Hwan Kim, Won-Sik Shin, Woong Lee
-
Publication number: 20070026651Abstract: In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the insulating pattern. The first silicon layer has an opened seam overlying the previously exposed portion of the substrate. A heat treatment on the substrate is performed at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed via the silicon migration. A second silicon layer is then formed on the first silicon layer. Thus, surface profile of a floating gate electrode obtained from the first and second silicon layers may be improved.Type: ApplicationFiled: July 5, 2006Publication date: February 1, 2007Inventors: Hun-Hyeoung Leam, Hyeon-Deok Lee, Young-Sub You, Won-Jun Jang, Woong Lee, Jung-Hyun Park, Sang-Kyoung Lee, Jung-Geun Jee, Sang-Hoon Lee
-
Publication number: 20060261842Abstract: A plurality of gate lines are formed on an insulating substrate in the horizontal direction, a gate shorting bar connected to the data lines is formed in the vertical direction and a gate insulating film is formed thereon. A plurality of data lines intersecting the gate lines are formed on the gate insulating film in the vertical direction, and a data shorting bar connected to the data lines is formed outside the display region. A first shorting bar is formed on the gate insulating film, located between the gate lines and the gate shorting bar, and connected to the odd gate lines. A second secondary shorting bar is formed parallel to the first shorting bar and connected to the even gate lines.Type: ApplicationFiled: July 24, 2006Publication date: November 23, 2006Inventors: Sang-Kyoung Lee, Dong-Gyu Kim, Min-Hyung Moon
-
Patent number: 7081770Abstract: A plurality of gate lines are formed on an insulating substrate in the horizontal direction, a gate shorting bar connected to the data lines is formed in the vertical direction and a gate insulating film is formed thereon. A plurality of data lines intersecting the gate lines are formed on the gate insulating film in the vertical direction, and a data shorting bar connected to the data lines is formed outside the display region. A first shorting bar is formed on the gate insulating film, located between the gate lines and the gate shorting bar, and connected to the odd gate lines. A second secondary shorting bar is formed parallel to the first shorting bar and connected to the even gate lines.Type: GrantFiled: November 15, 2005Date of Patent: July 25, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Kyoung Lee, Dong-Gyu Kim, Min-Hyung Moon
-
Publication number: 20060061381Abstract: A plurality of gate lines are formed on an insulating substrate in the horizontal direction, a gate shorting bar connected to the data lines is formed in the vertical direction and a gate insulating film is formed thereon. A plurality of data lines intersecting the gate lines are formed on the gate insulating film in the vertical direction, and a data shorting bar connected to the data lines is formed outside the display region. A first shorting bar is formed on the gate insulating film, located between the gate lines and the gate shorting bar, and connected to the odd gate lines. A second secondary shorting bar is formed parallel to the first shorting bar and connected to the even gate lines.Type: ApplicationFiled: November 15, 2005Publication date: March 23, 2006Inventors: Sang-Kyoung Lee, Dong-Gyu Kim, Min-Hyung Moon
-
Patent number: RE41873Abstract: A plurality of gate lines are formed on an insulating substrate in the horizontal direction, a gate shorting bar connected to the data lines is formed in the vertical direction and a gate insulating film is formed thereon. A plurality of data lines intersecting the gate lines are formed on the gate insulating film in the vertical direction, and a data shorting bar connected to the data lines is formed outside the display region. A first shorting bar is formed on the gate insulating film, located between the gate lines and the gate shorting bar, and connected to the odd gate lines. A second secondary shorting bar is formed parallel to the first shorting bar and connected to the even gate lines.Type: GrantFiled: December 29, 2006Date of Patent: October 26, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Kyoung Lee, Dong-Gyu Kim, Min-Hyung Moon