Abstract: A hair dye dispenser according to an embodiment of the present invention includes a housing having an opening hole formed on one side of which a hair dye is provided, a plurality of cartridges disposed inside the housing and accommodating at least one dyeing material, a main body in which the plurality of cartridges are rotatably disposed, a main motor for rotating the main body so that a first cartridge of the plurality of cartridges is located adjacent to the opening hole, a discharge module for discharging the dyeing material contained in the first cartridge, and an accommodating body in which a basket accommodating the dyeing material discharged by the discharge module is placed, wherein the discharge module may include an elevating body that pressurizes the first cartridge when moving up and is separated from the first cartridge when moving down.

Abstract: Disclosed are semiconductor devices and semiconductor packages. The semiconductor device comprises a semiconductor substrate that includes a stack region and a pad region, a peripheral circuit structure that includes a plurality of peripheral circuits on the semiconductor substrate, a cell array structure on the peripheral circuit structure, and a redistribution layer on the cell array structure and including a redistribution dielectric layer and a redistribution pattern on the redistribution dielectric layer. The redistribution dielectric layer covers an uppermost conductive pattern of the cell array structure. The redistribution pattern is connected to the uppermost conductive pattern. A thickness in a vertical direction of the redistribution layer on the pad region is greater than that of the redistribution layer on the stack region.

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

Abstract: A nonvolatile memory device includes a first memory cell array, a first bi-directional multiplexer, a first register, a second register, a first I/O pad and a second I/O pad. The first memory cell array stores first data. The first bi-directional multiplexer receives the first data and distributes the first data into first sub-data and second sub-data. The first register stores first sub-data from the first bi-directional multiplexer. The second register stores second sub-data from a second bi-directional multiplexer. The first I/O pad outputs the first sub-data from the first register to outside. The second I/O pad outputs the second sub-data from the second register to the outside.

Abstract: A nonvolatile memory device includes a first memory cell array, a first bi-directional multiplexer, a first register, a second register, a first I/O pad and a second I/O pad. The first memory cell array stores first data. The first bi-directional multiplexer receives the first data and distributes the first data into first sub-data and second sub-data. The first register stores first sub-data from the first bi-directional multiplexer. The second register stores second sub-data from a second bi-directional multiplexer. The first I/O pad outputs the first sub-data from the first register to outside. The second I/O pad outputs the second sub-data from the second register to the outside.

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

Abstract: A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).

Abstract: A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).

Abstract: A clock signal processor includes a duty cycle corrector, a switch point calculator, and a multiplexer. The duty cycle corrector generates a second clock signal by modifying a duty cycle of a first clock signal. The switch point calculator activates a switch signal at an end of a latency period in which a read command is provided to a non-volatile memory device and an invalid data is read from the non-volatile memory device. The multiplexer outputs one of the first and second clock signals as a third clock signal based on the switch signal.

Abstract: A clock signal processor includes a duty cycle corrector, a switch point calculator, and a multiplexer. The duty cycle corrector generates a second clock signal by modifying a duty cycle of a first clock signal. The switch point calculator activates a switch signal at an end of a latency period in which a read command is provided to a non-volatile memory device and an invalid data is read from the non-volatile memory device. The multiplexer outputs one of the first and second clock signals as a third clock signal based on the switch signal.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of cell strings each having a plurality of memory cells stacked in a direction perpendicular to a substrate, and a peripheral circuit region including a plurality of transistors electrically connected to the memory cell array through a plurality of conductive lines. Each of the transistors includes a gate electrode crossing an active region of the substrate in a first direction and source and drain regions in the active region at the opposite sides of the gate electrode. In at least one of the transistors, the number of source contact plugs connected to the source region is different from the number of drain contact plugs connected to the drain region.