Abstract: Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse.

Abstract: Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse.

Abstract: A semiconductor memory device and related test method are disclosed. Test data is defined from a group of M test bits selected from either input data or corresponding output data. A parallel bit test is then conducted on the test data. The M test bits include N test bits, where N is less than M, selected on a bit by bit basis from the output data, and L test bits, where N+L=M, selected from the input data. The selection of input data may be made in accordance with a don't care case for selected test data.

Abstract: A semiconductor memory device performs a parallel bit test on a plurality of memory blocks by writing test pattern data into the plurality of memory blocks, outputting two bits from each memory block in parallel and comparing the two bits output from each memory block with each other in a first test mode, and outputting two bits from respectively different memory blocks and comparing the two bits output from the respectively different memory blocks with each other in a second test mode.

Abstract: In a method of inputting/outputting data in a semiconductor memory device, first data and second data are buffered and outputted to a first output node and a second output node, respectively, in a normal mode. In a test mode, the first data is buffered through a first transmission line and a second transmission line and outputted to the first output node and the second output node in response to at least one control signal. Also, in the test mode, the second data is buffered through the first transmission line and the second transmission line and outputted to the first output node and the second output node in response to the at least one control signal. Accordingly, test time may be reduced, and variations of operation characteristics caused by merging the data pins may also be reduced.

Abstract: A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable of writing non-identical data to data input/output pads of each group when data is written to the memory cell array.

Abstract: A bit line sense amplifier and method thereof are provided. The example bit line sense amplifier may include a sense amplifying circuit coupled between a first bit line and a second bit line. The sense amplifying circuit may be configured to amplify a voltage difference between the first bit line and the second bit line. The example bit line sense amplifier may further include a power supply voltage providing circuit configured to provide a first power supply voltage and a second power supply voltage to the sense amplifying circuit in response to first and second bit line sensing control signals. The bit line sense amplifier may further include a bit line voltage compensation circuit configured to prevent a voltage-reduction at the first bit line and the second bit line for a delay period, the delay period including at least a period of time after a pre-charging of the first and second bit lines, in response to one or more of the first and second bit line sensing control signals.

Abstract: A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable of writing non-identical data to data input/output pads of each group when data is written to the memory cell array.

Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including regular cells; a redundancy memory cell array including redundancy cells for substituting for defective regular cells; a command decoder for generating an operation mode selection signal in response to command signals; a redundancy cell test controller for generating a test operation control signal and transmitting address signals in response to the operation mode selection signal; and a redundancy decoder for decoding the address signals to select the redundancy cells in response to the test operation control signal. All redundancy cells can be selected and tested based on the external command signal and the address signal, and thus it is possible to check all redundancy cells for defects in advance even after the semiconductor memory device is packaged, and to enable only non-defective redundancy cells to be substituted for defective regular cells.

Abstract: An internal supply voltage generation circuit includes first and second driving circuits and a resistive device. The first driving circuit receives a feedback voltage from a first node and generates a first output voltage based on first and second reference voltages to provide the first output voltage to the first node. The first output voltage is maintained between the first and second reference voltages. The second driving circuit receives a feedback voltage from a second node voltage and generates a second output voltage based on third and fourth reference voltages to provide the second output voltage to the second node. The second output voltage is maintained between the third and fourth reference voltages, and the second output voltage of the second node is provided as an internal supply voltage. The resistive device is coupled between the first and second nodes.

Abstract: A semiconductor memory device and related test method are disclosed. Test data is defined from a group of M test bits selected from either input data or corresponding output data. A parallel bit test is then conducted on the test data. The M test bits include N test bits, where N is less than M, selected on a bit by bit basis from the output data, and L test bits, where N+L=M, selected from the input data. The selection of input data may be made in accordance with a don't care case for selected test data.

Abstract: A semiconductor memory device performs a parallel bit test on a plurality of memory blocks by writing test pattern data into the plurality of memory blocks, outputting two bits from each memory block in parallel and comparing the two bits output from each memory block with each other in a first test mode, and outputting two bits from respectively different memory blocks and comparing the two bits output from the respectively different memory blocks with each other in a second test mode.

Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including regular cells; a redundancy memory cell array including redundancy cells for substituting for defective regular cells; a command decoder for generating an operation mode selection signal in response to command signals; a redundancy cell test controller for generating a test operation control signal and transmitting address signals in response to the operation mode selection signal; and a redundancy decoder for decoding the address signals to select the redundancy cells in response to the test operation control signal. All redundancy cells can be selected and tested based on the external command signal and the address signal, and thus it is possible to check all redundancy cells for defects in advance even after the semiconductor memory device is packaged, and to enable only non-defective redundancy cells to be substituted for defective regular cells.

Abstract: An internal supply voltage generation circuit includes first and second driving circuits and a resistive device. The first driving circuit receives a feedback voltage from a first node and generates a first output voltage based on first and second reference voltages to provide the first output voltage to the first node. The first output voltage is maintained between the first and second reference voltages. The second driving circuit receives a feedback voltage from a second node voltage and generates a second output voltage based on third and fourth reference voltages to provide the second output voltage to the second node. The second output voltage is maintained between the third and fourth reference voltages, and the second output voltage of the second node is provided as an internal supply voltage. The resistive device is coupled between the first and second nodes.

Abstract: Provided is a semiconductor device including a plurality of fuse circuits. Each of the fuse circuits includes: a first signal generator generating a first signal to a first node in response to a power-up signal; a pull-down transistor pulling down a second node in response to the first signal; a pull-up transistor and a fuse which are connected in series between a power supply voltage and the second node and pulling up the second node in response to the first signal when the fuse is not cut; a buffer buffering a signal output from the second node and generating a control signal; and a standby reset transistor resetting the second node in response to the control signal output from the buffer, wherein the pull-down transistor and the standby reset transistor have threshold voltages lower than a threshold voltage of the buffer. Also, each of the fuse circuits further includes an active reset transistor resetting the second node in the active mode in response to the reset control signal.

Abstract: A bit line sense amplifier and method thereof are provided. The example bit line sense amplifier may include a sense amplifying circuit coupled between a first bit line and a second bit line. The sense amplifying circuit may be configured to amplify a voltage difference between the first bit line and the second bit line. The example bit line sense amplifier may further include a power supply voltage providing circuit configured to provide a first power supply voltage and a second power supply voltage to the sense amplifying circuit in response to first and second bit line sensing control signals. The bit line sense amplifier may further include a bit line voltage compensation circuit configured to prevent a voltage-reduction at the first bit line and the second bit line for a delay period, the delay period including at least a period of time after a pre-charging of the first and second bit lines, in response to one or more of the first and second bit line sensing control signals.

Abstract: A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable of writing non-identical data to data input/output pads of each group when data is written to the memory cell array.

Abstract: In a method of inputting/outputting data in a semiconductor memory device, first data and second data are buffered and outputted to a first output node and a second output node, respectively, in a normal mode. In a test mode, the first data is buffered through a first transmission line and a second transmission line and outputted to the first output node and the second output node in response to at least one control signal. Also, in the test mode, the second data is buffered through the first transmission line and the second transmission line and outputted to the first output node and the second output node in response to the at least one control signal. Accordingly, test time may be reduced, and variations of operation characteristics caused by merging the data pins may also be reduced.

Abstract: The semiconductor memory device includes a power supply voltage (Vcc) applied to the semiconductor device, a row controller for generating an output signal in response to a control signal representing one of a normal operation state and a stand-by state, and a plurality of row decoders connected between the row controller and a plurality of word lines. Each row decoder activates a corresponding word line in response to the output signal from the row controller and a row address signal from an external source, and the output signal of the row controller is a high voltage or a ground voltage when the plurality of row decoders are in a normal operation state or in a stand-by state, respectively. The semiconductor memory device also includes a column controller for generating an output signal in response to a first control signal representing one of a normal operation state and a stand-by state and a plurality of column decoders connected between the column controller and a plurality of column selection lines.