Abstract: A device for effectively and economically receiving a packet by eliminating temporary memory and a memory controller. The apparatus includes an inspection logic circuit for inspecting data units as soon as they arrive in order to find an error included in the packet and generating control signals according to a result of inspecting a data unit; a multiplexer for receiving data units and distributing the received data units as soon as the data units have arrived; and FIFO memories for receiving the data unit, storing the data unit in a corresponding one of FIFO memories and either deleting or completing storing data units according to the control signals from the inspection logic circuit. The present invention can reduce manufacturing cost of the device by eliminating a temporary memory and a memory controller for the temporary memory and can also reduce processing time.

Abstract: The present invention is a data transfer protocol control system with a host bus interface that includes a transmitting/receiving command DMA, a transmitting data DMA and a receiving data DMA for controlling data transfer protocol with a host bus interface considering characteristic, usage frequency, simultaneous processing functions of the command DMA and the data DMAs. A host interface bus is efficiently used and bus usage ratio is distributed properly to support transfer flow properly and improve the entire system performance.

Abstract: In a first-in first-out memory circuit using a standard cell library memory, a memory block includes N number of memories (N>1). A read pointer designates read addresses of the N number of memories. A write pointer designates write addresses of the N number of memories. A memory controller selects one from the N number of memories based on the read/write addresses, generates n number of read/write clock signals by demultiplying a clock signal by n (n=N, n>1) and sends the n number of read/write clock signals having a 1/n cycle difference to the N number of memories thereby inputting/outputting data.

Abstract: The present invention is a data transfer protocol control system with a host bus interface that includes a transmitting/receiving command DMA, a transmitting data DMA and a receiving data DMA for controlling data transfer protocol with a host bus interface considering characteristic, usage frequency, simultaneous processing functions of the command DMA and the data DMAs. A host interface bus is efficiently used and bus usage ratio is distributed properly to support transfer flow properly and improve the entire system performance.

Abstract: An apparatus for effectively and economically receiving packet by eliminating temporal memory and controller is disclosed. The apparatus includes; an inspection logic circuit for inspecting data units as soon as arrived in order to find error included in the packet and generating control signals according to a result of inspecting data unit; a multiplexer for receiving data units and distributing the received data units as soon as the data units are arrived; and a plurality of FIFO memories for receiving the data unit, storing the data unit in corresponding one of FIFO memories and deleting or completing to store data units according to the control signals from the inspection logic circuit. The present invention can reduce manufacturing cost of the apparatus by eliminating a temporal memory and a memory controller for the temporal memory and can also reduce a processing time.

Abstract: In a first-in first-out memory circuit using a standard cell library memory, a memory block includes N number of memories (N>1). A read pointer designates read addresses of the N number of memories. A write pointer designates write addresses of the N number of memories. A memory controller selects one from the N number of memories based on the read/write addresses, generates n number of read/write clock signals by demultiplying a clock signal by n (n=N, n>1) and sends the n number of read/write clock signals having a 1/n cycle difference to the N number of memories thereby inputting/outputting data.

Abstract: Disclosed herein is an interrupt redirection apparatus and method for inter-processor communication. The apparatus includes a plurality of ARM processors, a vectored interrupt controller, an interrupt command register, an interrupt data register for designating the contents of each interrupt, an interrupt signal generation unit, and a bus interface unit used for providing read and write accesses of both the interrupt command register and the interrupt data register. The vectored interrupt controller for receiving interrupts generated by hardware for performing a specific function under the control of each ARM processor and interrupts generated by peripheral hardware, and transferring each interrupt as each interrupt request signal to an ARM processor designated as a master processor. The interrupt command register designates targets and kinds of each interrupt to perform a function for receiving an interrupt redirection command and activating an interrupt request signal.

Abstract: Disclosed herein is an interrupt redirection apparatus and method for inter-processor communication. The apparatus includes a plurality of ARM processors, a vectored interrupt controller, an interrupt command register, an interrupt data register for designating the contents of each interrupt, an interrupt signal generation unit, and a bus interface unit used for providing read and write accesses of both the interrupt command register and the interrupt data register. The vectored interrupt controller for receiving interrupts generated by hardware for performing a specific function under the control of each ARM processor and interrupts generated by peripheral hardware, and transferring each interrupt as each interrupt request signal to an ARM processor designated as a master processor. The interrupt command register designates targets and kinds of each interrupt to perform a function for receiving an interrupt redirection command and activating an interrupt request signal.

Abstract: The present invention relates to a node connection apparatus. The 3-link node interconnection apparatus and parallel processing apparatus using the same confirm expanding nodes freely, only using fixed three connecting links, and are suitable to normal packaging method because of easy dividing into 2n (n>1) nodes. The apparatuses comprise the following nodes. The first node has three links connected to other nodes respectively. The second node has three links, one links of them is connected to the first node, and the other two links are in charge of connection of X+ direction, X− direction. The third node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Y+ direction, Y− direction. The fourth node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Z+ direction, Z− direction.

Abstract: An apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, includes: a node bus interface for interfacing with the node bus; an interconnection network interface for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; bus-side dual-port transaction buffers coupled between said node bus interface and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and network-side dual-port transaction buffers coupled between said interconnection network interface and said cache control logic for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.

Abstract: The present invention relates to a message-passing computer system and a packet-switched interconnection network. The message transfer apparatus in a packet-switched interconnection network includes a message send controller controlling a send procedure in which messages requested by a processor are sent via an output port, and a timer enabled by an output signal of the message send controller and generating a timeout signal. A buffer unit is connected to the message send controller and is composed of a message buffer having four buffers and a data buffer. A local bus controller connects the message send controller and the buffer unit to the local bus and controls a transfer request and a transfer response to the local bus. An output port controller connected to both the message send controller and the buffer unit controls the output port which sends a packet to an interconnection network.

Abstract: The present invention discloses a method for controlling a message send in a packet-switched interconnection network, which incorporates a message send controller supporting an efficient message send and a dedicated hardware capable of maximizing a message send rate, taking the structural characteristics of the message-passing parallel computer system method into maximum considerations, thereby minimizing software and hardware overhead in sending a message and being capable of selecting a message send method in accordance with the message characteristics.

Abstract: A message-passing multiprocessor system, such as, a network interface, a method for transferring messages between a node and a node, and a method for formatting the same in a message-passing computer system are disclosed herein. In the network interface for a computer system there are a plurality of nodes connected with one another through an interconnection network for communicating messages, and more than one processor, and a local shared memory, which are connected with one another through a node bus.