Patents by Inventor Sang-Moo Jeong

Sang-Moo Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10380943
    Abstract: An organic light emitting display device includes pixels connected to scan lines, data lines, and emission control lines to emit light components in response to amounts of current that flow from a first driving power source to a second driving power source, a sensing unit connected between the first or second driving power source and the pixels to measure to at least one of current and voltage, a controller to sense a control signal in response to at least one of the current and the voltage measured by the sensing unit, a timing controller to supply a plurality of emission start signals with different widths in a one frame period in response to the control signal when the organic light emitting display device is driven at a low frequency, and an emission driver to supply emission control signals to the emission control lines in response to the emission start signals.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 13, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang Moo Choi, Ji Hyun Ka, Won Kyu Kwak, Jin Jeon, Jin Tae Jeong
  • Patent number: 9953985
    Abstract: A method of manufacturing an integrated circuit device includes forming multilayered stack structures that extend parallel to and separated from one another on a substrate, followed by forming a buried conductive layer including a plurality of conductive line patterns that extend parallel to an extending direction of the multilayered stack structures and alternate with the multilayered stack structures; removing portions of the buried conductive layer to thereby separate the plurality of conductive line patterns of the buried conductive layer from one another as a plurality of contact plugs and, at the same time, form a plurality of insulating fence spaces that alternate with the plurality of contact plugs in the extending direction of the multilayered stack structures; and forming a plurality of insulating fences that fill the plurality of insulating fence spaces and include a plurality of insulating line patterns extending parallel to one another.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: April 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-gi Kim, Sang-moo Jeong, Seon-ju Kim, Hye-won Kim
  • Publication number: 20180012894
    Abstract: A method of manufacturing an integrated circuit device includes forming multilayered stack structures that extend parallel to and separated from one another on a substrate, followed by forming a buried conductive layer including a plurality of conductive line patterns that extend parallel to an extending direction of the multilayered stack structures and alternate with the multilayered stack structures; removing portions of the buried conductive layer to thereby separate the plurality of conductive line patterns of the buried conductive layer from one another as a plurality of contact plugs and, at the same time, form a plurality of insulating fence spaces that alternate with the plurality of contact plugs in the extending direction of the multilayered stack structures; and forming a plurality of insulating fences that fill the plurality of insulating fence spaces and include a plurality of insulating line patterns extending parallel to one another.
    Type: Application
    Filed: June 21, 2017
    Publication date: January 11, 2018
    Inventors: Hyun-gi KIM, Sang-moo JEONG, Seon-ju KIM, Hye-won KIM
  • Patent number: 7297998
    Abstract: According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit line and a bit line capping layer pattern stacked thereon. A buried contact interlayer insulating layer covers a surface of the semiconductor substrate having the two adjacent bit line patterns. A contact hole is placed in a portion between the bit line patterns to penetrate the buried contact interlayer insulating layer and the bit line interlayer insulating layer and to expose at least one side wall of the bit line patterns. A contact hole spacer covers side wall of the contact hole. A contact hole plug is placed on the contact hole spacer to fill the contact hole.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: November 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Goo Kim, Sang-Moo Jeong
  • Publication number: 20070059610
    Abstract: A semiconductor device with dummy patterns and methods of designing and making dummy patterns of a semiconductor device are provided. The method includes forming a first layout having main patterns, adding dot dummy patterns to the first layout to generate a second layout, and adding linked line/space dummy patterns to the second layout to generate a third layout. The dot dummy patterns may be oblique dot dummy patterns.
    Type: Application
    Filed: April 28, 2006
    Publication date: March 15, 2007
    Inventors: Sang-Moo Jeong, Sun-Hoo Park, Dong-Hyun Han
  • Publication number: 20060197162
    Abstract: According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit line and a bit line capping layer pattern stacked thereon. A buried contact interlayer insulating layer covers a surface of the semiconductor substrate having the two adjacent bit line patterns. A contact hole is placed in a portion between the bit line patterns to penetrate the buried contact interlayer insulating layer and the bit line interlayer insulating layer and to expose at least one side wall of the bit line patterns. A contact hole spacer covers side wall of the contact hole. A contact hole plug is placed on the contact hole spacer to fill the contact hole.
    Type: Application
    Filed: May 22, 2006
    Publication date: September 7, 2006
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-Goo KIM, Sang-Moo JEONG
  • Patent number: 7074718
    Abstract: According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit line and a bit line capping layer pattern stacked thereon. A buried contact interlayer insulating layer covers a surface of the semiconductor substrate having the two adjacent bit line patterns. A contact hole is placed in a portion between the bit line patterns to penetrate the buried contact interlayer insulating layer and the bit line interlayer insulating layer and to expose at least one side wall of the bit line patterns. A contact hole spacer covers side wall of the contact hole. A contact hole plug is placed on the contact hole spacer to fill the contact hole.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: July 11, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Goo Kim, Sang-Moo Jeong
  • Publication number: 20050017295
    Abstract: According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit line and a bit line capping layer pattern stacked thereon. A buried contact interlayer insulating layer covers a surface of the semiconductor substrate having the two adjacent bit line patterns. A contact hole is placed in a portion between the bit line patterns to penetrate the buried contact interlayer insulating layer and the bit line interlayer insulating layer and to expose at least one side wall of the bit line patterns. A contact hole spacer covers side wall of the contact hole. A contact hole plug is placed on the contact hole spacer to fill the contact hole.
    Type: Application
    Filed: July 22, 2004
    Publication date: January 27, 2005
    Inventors: Seong-Goo Kim, Sang-Moo Jeong
  • Patent number: 6124184
    Abstract: A method for forming an isolation region of a semiconductor device includes the steps of forming first and second insulating layers on a substrate, removing the second insulating layer over an isolation region, forming an oxide layer by oxidizing the first insulating layer over the isolation region, forming sidewall spacers at sides of the second insulating layer and over the isolation region, forming a trench by etching the oxide layer and the substrate at the isolation region, removing the sidewall spacers, forming a third insulating layer on the substrate in the trench, and forming an isolation layer in the trench.
    Type: Grant
    Filed: November 18, 1999
    Date of Patent: September 26, 2000
    Assignee: Hyundai Electronics Industries, Co.
    Inventor: Sang Moo Jeong