Abstract: Disclosed herein is a bidirectional shift register which is capable of preventing multi-outputs from both end stages. The shift register includes a plurality of stages for outputting scan pulses forward or reversely based on a start pulse and a plurality of clock pulses with a phase difference. A last one of the stages includes a forward scan controller for making a set node active and a reset node inactive based on any one of the clock pulses and a scan pulse from an upstream stage, a reverse scan controller for making the set node active and the reset node inactive based on any one of the clock pulses and the start pulse, and an output unit for outputting any one of a corresponding scan pulse and a deactivation voltage based on a voltage at the set node, a voltage at the reset node and any one of the clock pulses.

Abstract: Disclosed herein is a bidirectional shift register which is capable of preventing multi-outputs from both end stages. The shift register includes a plurality of stages for outputting scan pulses forward or reversely based on a start pulse and a plurality of clock pulses with a phase difference. A last one of the stages includes a forward scan controller for making a set node active and a reset node inactive based on any one of the clock pulses and a scan pulse from an upstream stage, a reverse scan controller for making the set node active and the reset node inactive based on any one of the clock pulses and the start pulse, and an output unit for outputting any one of a corresponding scan pulse and a deactivation voltage based on a voltage at the set node, a voltage at the reset node and any one of the clock pulses.

Abstract: Disclosed herein is a bidirectional shift register which is capable of preventing multi-outputs from both end stages. The shift register includes a plurality of stages for outputting scan pulses forward or reversely based on a start pulse and a plurality of clock pulses with a phase difference. A last one of the stages includes a forward scan controller for making a set node active and a reset node inactive based on any one of the clock pulses and a scan pulse from an upstream stage, a reverse scan controller for making the set node active and the reset node inactive based on any one of the clock pulses and the start pulse, and an output unit for outputting any one of a corresponding scan pulse and a deactivation voltage based on a voltage at the set node, a voltage at the reset node and any one of the clock pulses.

Abstract: Disclosed herein are signal transmission lines for an image display device and a method for wiring the same. The signal transmission lines include a plurality of control signal supply lines formed in a display panel in which at least one driving circuit is formed integrally with an image display region, such that the control signal supply lines are supplied with control signals for control of the driving circuit, respectively, and a plurality of control signal transmission lines formed in the display panel to cross the control signal supply lines and each electrically connected with at least one of the control signal supply lines, so as to transmit a corresponding one of the control signals to the driving circuit, wherein the control signal transmission lines have the same overlap areas with the control signal supply lines when they cross the control signal supply lines.

Abstract: Disclosed herein are signal transmission lines for an image display device and a method for wiring the same. The signal transmission lines include a plurality of control signal supply lines formed in a display panel in which at least one driving circuit is formed integrally with an image display region, such that the control signal supply lines are supplied with control signals for control of the driving circuit, respectively, and a plurality of control signal transmission lines formed in the display panel to cross the control signal supply lines and each electrically connected with at least one of the control signal supply lines, so as to transmit a corresponding one of the control signals to the driving circuit, wherein the control signal transmission lines have the same overlap areas with the control signal supply lines when they cross the control signal supply lines.