Abstract: Embodiments of apparatuses, methods, and systems for scheduling tasks to hardware threads are described. In an embodiment, a processor includes a multiple hardware threads and a task manager. The task manager is to issue a task to a hardware thread. The task manager includes a hardware task queue to store a descriptor for the task. The descriptor is to include a field to store a value to indicate whether the task is a single task, a collection of iterative tasks, and a linked list of tasks.

Abstract: Embodiments of apparatuses, methods, and systems for a multithreaded processor core with hardware-assisted task scheduling are described. In an embodiment, a processor includes a first hardware thread, a second hardware thread, and a task manager. The task manager is to issue a task to the first hardware thread. The task manager includes a hardware task queue in which to store a plurality of task descriptors. Each of the task descriptors is to represent one of a single task, a collection of iterative tasks, and a linked list of tasks.

Abstract: Optimized memory access bandwidth devices, systems, and methods for processing low spatial locality data are disclosed and described. A system memory is divided into a plurality of memory subsections, where each memory subsection is communicatively coupled to an independent memory channel to a memory controller. Memory access requests from a processor are thereby sent by the memory controller to only the appropriate memory subsection.

Abstract: Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to read K bits of M bits of encoded data in memory, D error detection bits, and P Parity bits protecting the M bits of encoded data for performing a read-write-modify (RWM) command operation on the K bits of the M bits encoded data, wherein K, M and D are positive integers and P is a vector of a set of parity bits. The memory controller can determine whether an error is present on the K bits of the M bits of encoded data according to the D error detection bits.

Abstract: An apparatus and method are described for reducing power when reading and writing graphics data. For example, one embodiment of an apparatus comprises: a graphics processor unit (GPU) to process graphics data including floating point data; a set of registers, at least one of the registers of the set partitioned to store the floating point data; and encode/decode logic to reduce a number of binary 1 values being read from the at least one register by causing a specified set of bit positions within the floating point data to be read out as 0s rather than 1s.

Abstract: An apparatus and method are described for reducing power when reading and writing graphics data. For example, one embodiment of an apparatus comprises: a graphics processor unit (GPU) to process graphics data including floating point data; a set of registers, at least one of the registers of the set partitioned to store the floating point data; and encode/decode logic to reduce a number of binary 1 values being read from the at least one register by causing a specified set of bit positions within the floating point data to be read out as 0s rather than 1s.

Abstract: Methods and apparatus relating to enhanced Data Bus Invert (EDBI) encoding for OR chained buses are described. In an embodiment, incoming data on a bus is encoded based at least in part on a determination of whether a next data value on the bus is going to transitioning from a valid value to a parked state. Other embodiments are also disclosed.

Abstract: A power converter is provided for an energy harvesting system of a micro-scale electronic device. The power converter is configured to transfer electrical energy from an energy transducer to an energy storage device. The power converter illustratively includes a tree topology charge pump.

Abstract: A power converter is provided for an energy harvesting system of a micro-scale electronic device. The power converter is configured to transfer electrical energy from an energy transducer to an energy storage device. The power converter illustratively includes a tree topology charge pump.