Abstract: A row address circuit of a semiconductor memory device includes a signal generator that generates a pulse in an enable signal for an output circuit that provides a decoded address. The pulse has a first edge that is delayed relative to a corresponding first edge of a refresh count signal and a second edge that precedes a corresponding second edge of the count signal. Accordingly, the enable signal prevents changes in the output signal that could otherwise result from input of an external address during a refresh operation. Therefore, the present invention can prevent an invalid address by cutting off a predecoder before a transition of a refresh count signal to prohibit a change of a predecoded output.

Abstract: A device and method for generating non-false interrupt signals are disclosed. They discriminate between noise and real signals from the interrupt sources. The device includes: plural signal generators for supplying indiscriminate interrupt demanding signals in response to signals from plural interrupt sources, respectively; plural counters for counting the indiscriminate interrupt demanding signals from the signal generators, respectively, to produce count values; plural comparators for comparing reference values against the counts to produce authenticated interrupt demanding signals, respectively; and a priority determining unit for receiving the authenticated interrupt demanding signals, for determining the relative priorities of these signals, and for issuing interrupt signals according to the priorities.

Abstract: A device and method for generating an interrupt for a microcontroller (MCU) are disclosed.