Patents by Inventor Sang Seok Lee
Sang Seok Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200167144Abstract: A method and apparatus configured for updating vehicle software using over-the-air (OTA) may include extracting first format difference data and second format difference data, corresponding to a first format and a second format of an update target software image, respectively, comparing the first format difference data and the second format difference data, determining a format of difference data as a transmission target, based on the comparison result, and transmitting the determined format of difference data to an update target vehicle terminal through a wireless network. Accordingly, it is advantageous to minimize the amount of transmitted data while vehicle software is updated using OTA.Type: ApplicationFiled: April 2, 2019Publication date: May 28, 2020Applicants: Hyundai Motor Company, Kia Motors CorporationInventors: Hye Won You, Sang Seok Lee, Young Woo Park
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Patent number: 10629744Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.Type: GrantFiled: May 31, 2018Date of Patent: April 21, 2020Assignee: Electronics and Telecommunications Research InstituteInventors: Kyoung Ik Cho, Jae Bon Koo, Chan Woo Park, Bock Soon Na, Sang Seok Lee, Sang Chul Lim, Soon-Won Jung, Hye Yong Chu
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Patent number: 10615167Abstract: A memory device includes a main one-time programmable (OTP) memory cell connected to a main word line and a main bit line; a redundant OTP memory cell connected to a redundant word line and a redundant bit line; and an input/output circuit configured to, during a program operation to program the main OTP memory cell and the redundant OTP memory cell, electrically separate the main bit line and the redundant bit line and form a first program current path to the main bit line and a second program current path to redundant bit line, wherein the first program current path and the second program current path are independent from each other.Type: GrantFiled: December 20, 2017Date of Patent: April 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Sang-Seok Lee
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Publication number: 20200006611Abstract: A light emitting device includes a substrate extending in a first direction and a second direction, first through fourth light emitting structures spaced apart from each other in the first and second direction and arranged in a matrix form on the substrate, a plurality of first interconnection layer structures connecting the first light emitting structure to the second light emitting structure, a second interconnection layer structure connecting the second light emitting structure to the third light emitting structure, and a plurality of third interconnection layer structures connecting the third light emitting structure to the fourth light emitting structure.Type: ApplicationFiled: March 20, 2019Publication date: January 2, 2020Inventors: Min-gu Ko, Jung-hee Kwak, Young-ho Ryoo, Seong-seok Yang, Sang-seok Lee, Seung-wan Chae
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Patent number: 10199118Abstract: A one-time programmable (OTP) memory device includes an OTP cell array, a latch controller, a column selection circuit, and a latch circuit. The OTP cell array includes a plurality of OTP memory cells respectively connected to a plurality of bitlines. The latch controller generates a latch address signal indicating an address that is changed sequentially in an enable mode to initialize the OTP memory device. The column selection circuit electrically connects a plurality of bitline groups of the bitlines to a plurality of input-output lines sequentially based on the latch address signal in the enable mode. The latch circuit receives and stores fuse bits provided sequentially through the bitline groups and the input-output lines in the enable mode.Type: GrantFiled: July 24, 2017Date of Patent: February 5, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Seok Lee, Hyun-Taek Jung
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Patent number: 10177278Abstract: A semiconductor light emitting device includes: a multilayer semiconductor body having a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, an active layer between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, and at least one recess exposing the first conductivity-type semiconductor layer, and an insulating part on an internal sidewall of the at least one recess and an upper surface of the second conductivity-type semiconductor layer. The insulating part has an insulating spacer on the internal sidewall of the recess, and a lateral surface of the insulating spacer has a surface without an angular point from an upper end to a lower end thereof.Type: GrantFiled: February 21, 2017Date of Patent: January 8, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju Hyun Kim, Jae Ryung Yoo, Gi Bum Kim, Ha Yeong Son, Sang Seok Lee
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Publication number: 20180358369Abstract: A memory device includes a main one-time programmable (OTP) memory cell connected to a main word line and a main bit line; a redundant OTP memory cell connected to a redundant word line and a redundant bit line; and an input/output circuit configured to, during a program operation to program the main OTP memory cell and the redundant OTP memory cell, electrically separate the main bit line and the redundant bit line and form a first program current path to the main bit line and a second program current path to redundant bit line, wherein the first program current path and the second program current path are independent from each other.Type: ApplicationFiled: December 20, 2017Publication date: December 13, 2018Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Sang-Seok LEE
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Patent number: 10128425Abstract: A semiconductor light emitting device includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer; and an insulating layer on the light emitting structure and including first and second through-holes. The insulating layer includes a first lower insulating layer and a second lower insulating layer. The first insulating layer is disposed on the first conductivity-type semiconductor layer and is surrounded by the second lower insulating layer with the first through-hole interposed therebetween.Type: GrantFiled: January 5, 2018Date of Patent: November 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon Woo Jeon, Sang Seok Lee, Hyun Kwon Hong
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Publication number: 20180277684Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.Type: ApplicationFiled: May 31, 2018Publication date: September 27, 2018Applicant: Electronics and Telecommunications Research InstituteInventors: Kyoung Ik CHO, Jae Bon KOO, Chan Woo PARK, Bock Soon NA, Sang Seok LEE, Sang Chul LIM, Soon-Won JUNG, Hye Yong CHU
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Patent number: 10026844Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.Type: GrantFiled: March 17, 2017Date of Patent: July 17, 2018Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Kyoung Ik Cho, Jae Bon Koo, Chan Woo Park, Bock Soon Na, Sang Seok Lee, Sang Chul Lim, Soon-Won Jung, Hye Yong Chu
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Publication number: 20180130932Abstract: A semiconductor light emitting device includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer; and an insulating layer on the light emitting structure and including first and second through-holes. The insulating layer includes a first lower insulating layer and a second lower insulating layer. The first insulating layer is disposed on the first conductivity-type semiconductor layer and is surrounded by the second lower insulating layer with the first through-hole interposed therebetween.Type: ApplicationFiled: January 5, 2018Publication date: May 10, 2018Inventors: Joon Woo JEON, Sang Seok LEE, Hyun Kwon HONG
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Publication number: 20180108425Abstract: A one-time programmable (OTP) memory device includes an OTP cell array, a latch controller, a column selection circuit, and a latch circuit. The OTP cell array includes a plurality of OTP memory cells respectively connected to a plurality of bitlines. The latch controller generates a latch address signal indicating an address that is changed sequentially in an enable mode to initialize the OTP memory device. The column selection circuit electrically connects a plurality of bitline groups of the bitlines to a plurality of input-output lines sequentially based on the latch address signal in the enable mode. The latch circuit receives and stores fuse bits provided sequentially through the bitline groups and the input-output lines in the enable mode.Type: ApplicationFiled: July 24, 2017Publication date: April 19, 2018Inventors: Sang-Seok LEE, Hyun-Taek JUNG
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Patent number: 9905309Abstract: A one-time programmable (OTP) memory device includes an OTP memory cell array comprising a plurality of dummy cells and a plurality of main cell groups of main cells and an access circuit configured to write data to at least two of the cells simultaneously. The arrangement of the dummy cells and the main cell groups may allow for the reliable writing of multi-bit data to the memory array. Each of the main cell groups may include a plurality of main cells which are connected to word lines, respectively, and to bit lines, respectively. Each of the main cells may be writable and each of the dummy cells may be unwritable. Each of the main cells may include a contact layer, and the dummy cells might not include the contact layer. A supply voltage may be applied to the OTP memory cell array through the contact layer.Type: GrantFiled: December 29, 2016Date of Patent: February 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Hoon Jin Bang, Sang Seok Lee
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Publication number: 20180040788Abstract: A semiconductor light emitting device includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer; and an insulating layer on the light emitting structure and including first and second through-holes. The insulating layer includes a first lower insulating layer and a second lower insulating layer. The first insulating layer is disposed on the first conductivity-type semiconductor layer and is surrounded by the second lower insulating layer with the first through-hole interposed therebetween.Type: ApplicationFiled: February 27, 2017Publication date: February 8, 2018Inventors: Joon Woo JEON, Sang Seok LEE, Hyun Kwon HONG
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Patent number: 9887334Abstract: A semiconductor light emitting device includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer; and an insulating layer on the light emitting structure and including first and second through-holes. The insulating layer includes a first lower insulating layer and a second lower insulating layer. The first insulating layer is disposed on the first conductivity-type semiconductor layer and is surrounded by the second lower insulating layer with the first through-hole interposed therebetween.Type: GrantFiled: February 27, 2017Date of Patent: February 6, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon Woo Jeon, Sang Seok Lee, Hyun Kwon Hong
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Publication number: 20180019380Abstract: A semiconductor light emitting device includes: a multilayer semiconductor body having a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, an active layer between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, and at least one recess exposing the first conductivity-type semiconductor layer, and an insulating part on an internal sidewall of the at least one recess and an upper surface of the second conductivity-type semiconductor layer. The insulating part has an insulating spacer on the internal sidewall of the recess, and a lateral surface of the insulating spacer has a surface without an angular point from an upper end to a lower end thereof.Type: ApplicationFiled: February 21, 2017Publication date: January 18, 2018Inventors: Ju Hyun KIM, Jae Ryung YOO, Gi Bum KIM, Ha Yeong SON, Sang Seok LEE
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Publication number: 20180012861Abstract: Provided is a method of manufacturing an electronic apparatus which includes preparing a substrate having a first Young's modulus, disposing a thin film having a second Young's modulus greater than the first Young's modulus on the substrate, disposing an electronic device on the thin film, and disposing a capping layer configured to cover the electronic device on the thin film.Type: ApplicationFiled: June 23, 2017Publication date: January 11, 2018Applicant: Electronics and Telecommunications Research InstituteInventors: Ji-Young OH, Joo Yeon KIM, Jae Bon KOO, Bock Soon NA, Nae-Man PARK, Chan Woo PARK, Sang Seok LEE, Soon Won JUNG, Chi-Sun HWANG, Keunsoo LEE
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Patent number: 9864251Abstract: Provided is a color changeable device which includes a first substrate and a second substrate that are spaced apart from each other, a first transparent electrode disposed on the first substrate, a second transparent electrode disposed on the second substrate, an electrochromic layer disposed between the first transparent electrode and the second transparent electrode, an organic layer disposed between the first transparent electrode and the electrochromic layer. The organic layer may include a hole injection layer or an electron injection layer. The organic layer may further include a hole transport layer or an electron transport layer.Type: GrantFiled: January 27, 2016Date of Patent: January 9, 2018Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ji-Young Oh, Jae Bon Koo, Joo Yeon Kim, Bock Soon Na, Chan Woo Park, Sang Seok Lee, Soon-Won Jung, Seong-Mok Cho, Hye Yong Chu
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Patent number: 9865559Abstract: Provided is a method for manufacturing a stretchable wire, the method including removing a portion of a photoresist layer on a substrate to form a photoresist pattern comprising at least one pattern slit, applying a liquid-phase conductive material on the photoresist pattern to form a liquid-phase conductive structure in the pattern slit, forming a stretchable first insulating layer on the liquid-phase conductive structure, after removing the photoresist pattern, and separating the liquid-phase conductive structure and the first insulating layer from the substrate.Type: GrantFiled: July 26, 2016Date of Patent: January 9, 2018Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Chan Woo Park, Jae Bon Koo, Bock Soon Na, Rae-Man Park, Ji-Young Oh, Sang Seok Lee, Soon-Won Jung
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Patent number: 9842669Abstract: A stretchable wire including a stretchable solid-phase conductive structure; a stretchable insulation layer which surrounds the solid-phase conductive structure; and a liquid-phase conductive material layer disposed between the solid-phase conductive structure and the stretchable insulation layer, and in contact with the solid-phase conductive structure, and a method of fabricating the same.Type: GrantFiled: July 27, 2016Date of Patent: December 12, 2017Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Chan Woo Park, Jae Bon Koo, Bock Soon Na, Rae-Man Park, Ji-Young Oh, Sang Seok Lee, Soon-Won Jung